Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restoring a microarchitecture state of the functional circuitry of the first chip. The method includes initializing a system state of the semiconductor device and entering a wait state for a state capture triggering event. In response to an occurrence of a state capture triggering event, state data representing a current system state of the functional circuitry on the first chip is captured. The captured state data is transferred to the second chip through a system state I/O (input/output) interface of the second chip under control of the control circuitry on the second chip. A copy of the captured state data is then stored in a memory.

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.