Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

Abstract: An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

Abstract: Nitrogen is piled-up at a top interface of a gate dielectric layer by a process of the present invention. A gate dielectric layer (14) is formed on a substrate (12). A buffer layer (16), such as polysilicon, is formed on the dielectric layer. A nitrogen source layer (18), such as oxynitride, is formed on the buffer layer. The device is annealed to drive nitrogen from the source layer through the buffer layer and to an interface (15) between the polysilicon and the dielectric, resulting in a high nitrogen concentration at this interface. A nitrogen concentration may also be achieved at an interface (13) between the dielectric layer and the substrate.

Abstract: A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).

Abstract: A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

Abstract: A semiconductor substrate is denuded using a reducing gas mixture including carbon monoxide and carbon dioxide. Use of the reducing gas mixture allows very low oxygen partial pressure to be achieved in a furnace tube during the step of denuding. Oxygen partial pressure lower than 1E-9 atmosphere may be achieved by adjusting the relative ratio of carbon monoxide and carbon dioxide. Precipitates are grown after forming nucleating sites. Both CZ and FZ substrates may use the process, and the process can be used with silicon, germanium, or other semiconductor materials.

Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Abstract: Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.

Abstract: A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by mass analysis and are accelerated into a hydrogen-free plasma. A reaction occurs between energized atoms within the plasma and the energized silicon ions resulting in the deposition of a thin film on the semiconductor substrate.

Abstract: An improved LOCOS isolation process is disclosed wherein an oxidizable layer is conformably dieposited to overlie a silicon nitride oxidation mask. In accordance with one embodiment of the invention, a composite layer comprising a buffer layer and an oxidation resistant material is patterned to form an oxidation mask on a silicon substrate. A layer of an oxidizable material is conformably deposited to overlie the oxidation mask. During the oxidation process used to form electrical isolation structures in the substrate, a substantial reduction in lateral oxidation encroachment is realized.

Abstract: A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polycrystalline silicon is lightly doped or undoped and the top layer is heavily doped to increase the conductivity of the electrode. The barrier layer impedes the diffusion of conductivity determining dopant impurities from one layer of polycrystalline silicon to the other.

Abstract: An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon providing an etching endpoint during the anisotropic etching used for sidewall formation. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the pad oxide. A first nitride layer, to be used for oxidation masking during field oxide growth, is deposited overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer.The first nitride layer and second polysilicon layer are patterned by conventional lithography while the first polysilicon and pad oxide layers remained unpatterned.

Abstract: A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening.

Abstract: A technique for selectively implanting regions of semiconductor crystals with oxygen to increase their yield strength. This intentional, selective oxygen pinning technique is especially useful in causing underlying, originally oxygen-free silicon to be more resistant to plastic deformation during isolation field oxide formation processes. Oxide regions grown on a substrate cause stress at the oxide/substrate interface and typically dislocation and other stress induced crystallographic defects at and near the point of stress, especially if the substrate is essentially oxygen-free. Dislocation and other crystallographic defects that occur in the areas of device formation and p/n junctions can cause junction leakage and active device degradation.

Abstract: A process for selective deposition of a refractory metal such as tungsten at high temperatures and low pressure via chemical vapor deposition during semiconductor device manufacturing is provided. A dielectric layer is nitrided by chemical deposition of a nitrogen bearing gas prior to LPCVD deposition of tungsten for purposes such as contact metallization of current conducting electrodes and current controlling electrodes of transistors. Since nitridation of the dielectric is a surface chemical reaction and not an addition of material to the dielectric, no additional complexity is introduced into the LPCVD process. The refractory metal does not substantially deposit on the nitrided dielectric thereby providing selective metal deposition.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: A process is disclosed for preparing silicon wafers having a high quality, high lifetime surface layer and a bulk region characterized by a low lifetime and by a high density of precipitated oxygen gettering sites. A wafer having a relatively high concentration of interstitial oxygen is heated in a reducing ambient at a sufficiently high temperature and a sufficiently long time to cause a surface layer to be denuded of oxygen related defects and dislocations. The temperature is then ramped down to a lower temperature and the wafer is maintained at this lower temperature for a sufficient time to allow precipitation of oxygen within the bulk of the wafer.