Abstract: An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

Abstract: A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.

Abstract: A circuit and method degrades throughput of floating point operations within a computing system. At the time of manufacture a preprogrammed value is stored. This may be done, for example, using fusible links, separate metal layers, internal bonding pad selection, EPROM/OTP memory cells, ion milling, laser evaporation and external programming pins. When a floating point processor processes a floating point operation, operation of a main processor is delayed an amount corresponding to the preprogrammed value. For example, when the floating point processor processes a floating point operation, a counter begins to count. Operation of the main processor is delayed until the counter has counted to a number equal to the preprogrammed value. Upon the counter completing counting to a number equal to the preprogrammed value, normal operation of the main processor is resumed.