Abstract: A motor head cover for a roller shade that has an electric motor releasably secured to an end bracket by an insert plate. The motor head cover has a C-shaped body having a mouth opening and an outer circumferential surface. The outer circumferential surface has an inner body surface, an outer body surface, an outer, inwardly directed, side surface, and an inner, inwardly directed, side surface. Each of the side surfaces extend inwardly from the circumferential surface at approximately 90 degrees to collectively form a raceway with the inner body surface. The inner, inwardly directed, side surface is configured to be engaged about a circumferential lip on the insert plate to assist in releasably securing the motor head cover thereto. The inner, inwardly directed side surface, has a series of spaced apart notches that assist in a non-destructive flexure of the motor head cover when securing about the insert plate.

Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Abstract: A processor configured to execute one or more virtual machines (VMs) includes an input-output memory management unit (IOMMU) configured to handle memory-mapped input-output (MMIO) requests and direct memory access (DMA) requests from a processor core of the processor or one or more input/output (I/O) devices. In response to receiving an MMIO or DMA request, the IOMMU is configured to determine a VM associated with the request. The IOMMU then checks a security indicator field of an address space identifier (ASID) mask table to determine if the VM was previously the target of an attack by a malicious entity. In response to the VM previously being a target of an attack, the IOMMU denies the received MMIO or DMA request.

Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.

Abstract: The disclosed device includes a direct memory access (DMA) engine having multiple backends and a frontend. The frontend receives a memory operation command, selects one of the backends based on an affinity of the selected backend corresponding to the memory operation command, and instructing the selected backend to perform the memory operation command. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An apparatus and method for efficiently performing remote memory access requests among multiple processing nodes. In various implementations, a computing system has a first node and a second node. Each of these nodes has a corresponding virtual address space in the computing system, and each node assigns subdivisions of the virtual address spaces to multiple clients of the node. The nodes assign a subset of a first virtual address space of a first client in the first node to remote data stored in a second virtual address space of a second client in the second node. Remote presence check (RPC) circuits of the nodes assign the second virtual address space to a subset of a network physical address (NPA) space. The RPC circuits of the nodes use assignments to the NPA space to verify that address mappings in TLBs are still available prior to routing memory access requests.

Abstract: The disclosed device includes a collectives engine that can offload collectives communications of multiple nodes and perform collective operations. The collectives engine can manage a direct mapping scheme of local memories of the nodes for access by the collectives engine. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computing device comprises a processor, a table walker, and a memory storing a segmented reverse map table in multiple non-contiguous portions of the memory. The table walker is configured to translate a virtual memory address specified by a memory access request to a physical memory address associated with the virtual memory address; and provide a requester associated with the memory access request with access to the associated physical memory address in response to an indication at the reverse map table that the requester is authorized to access the associated physical memory address.

Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.

Abstract: The tensioner is mounted in use to a vertical surface for throughpassage in taut relation of a clutch actuator selected from ball chain and cord and comprises a lock arrangement which: includes a plunger having a bearing surface; and, in use, is adapted to arrest throughpassage of the actuator in slack conditions. The plunger, in use, is: (i) adapted for vertical movement between an extended position and a retracted position that is elevated in relation to the extended position; adapted, when in the retracted position, to receive the actuator in the manner of a pulley, for smooth operation of the shade; and biased for movement towards the extended position. The lock arrangement is adapted, in use: upon movement of the plunger to the extended position, to arrest movement of the plunger towards the retracted position; and, when the plunger is in the extended position, to arrest throughpassage of the actuator.

Abstract: The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Abstract: A processor supports managing DMA accesses, in secure fashion, at an IOMMU. The IOMMU is configured to ensure that, for a given DMA request issued by an I/O device and associated with a particular executing VM, the device is bound to the VM according to a specified security registration process, and the request is targeted to a region of memory that has been assigned to the VM. The IOMMU thus prevents a malicious entity from accessing confidential information of a VM via DMA requests.

Abstract: An apparatus translates transaction requests using a bus protocol translation lookup table (LUT) that comprises bus protocol translation data. A bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation LUT. The controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. Associated methods are also presented. In some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

Abstract: An electronic device includes a processor that executes one or more guest operating systems and an input-output memory management unit (IOMMU). The IOMMU accesses, for/on behalf of each guest operating system among the one or more guest operating systems, IOMMU memory-mapped input-output (MMIO) registers in a separate copy of a set of IOMMU MMIO registers for that guest operating system.

Abstract: An apparatus translates transaction requests using a bus protocol translation lookup table (LUT) that comprises bus protocol translation data. A bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation LUT. The controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. Associated methods are also presented. In some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.

Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.