Patents by Inventor Philip Ng
Philip Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111688Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Omar Fakhri Ahmed, Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Jason Todd Arbaugh, Milind Baburao Kamble, Philip Ng, Xiaojian Liu
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Patent number: 11886367Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window.Type: GrantFiled: December 8, 2021Date of Patent: January 30, 2024Assignee: ATI Technologies ULCInventors: Michael E. McLean, Philip Ng
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Patent number: 11860797Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.Type: GrantFiled: December 30, 2021Date of Patent: January 2, 2024Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Nippon Raval, David A. Kaplan, Donald P. Matthews, Jr.
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Publication number: 20230376438Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Philip Ng, Vinay Patel
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Publication number: 20230313610Abstract: A shroud for the drive chain of a roller blind. The drive chain has s a series of balls mounted on a cord or wire and is in the form of a pair of leg members forming a loop. The shroud comprises an elongate body having opposed open ends with an internal passageway extending therebetween. The body has an enclosed exterior surface extending between the open ends. A longitudinal internal baffle may extend between the open ends, segmenting the internal passageway into two longitudinal channels, each channel extending between the open ends and dimensioned to slidably receive one of the pair of chain leg members therethrough. The baffle may have a longitudinal slot extending along its length, where the slot is dimensioned to permit the receipt of the cord or wire of the drive chain, and is dimensioned to preclude the passage of the balls of the drive chain therethrough.Type: ApplicationFiled: December 23, 2022Publication date: October 5, 2023Applicant: ZMC Metal Coating, Inc.Inventor: Philip NG
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Publication number: 20230315625Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: NIPPON RAVAL, PHILIP NG, ROSTISLAV S. DOBRIN
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Publication number: 20230313607Abstract: A shroud for the drive chain of a roller blind. The drive chain has s a series of balls mounted on a cord or wire and is in the form of a pair of leg members forming a loop. The shroud comprises an elongate body having opposed open ends with an internal passageway extending therebetween. The body has an enclosed exterior surface extending between the open ends. A longitudinal internal baffle may extend between the open ends, segmenting the internal passageway into two longitudinal channels, each channel extending between the open ends and dimensioned to slidably receive one of the pair of chain leg members therethrough. The baffle may have a longitudinal slot extending along its length, where the slot is dimensioned to permit the receipt of the cord or wire of the drive chain, and is dimensioned to preclude the passage of the balls of the drive chain therethrough.Type: ApplicationFiled: April 26, 2022Publication date: October 5, 2023Applicant: ZMC Metal Coating, Inc.Inventor: Philip NG
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Patent number: 11726693Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.Type: GrantFiled: December 29, 2020Date of Patent: August 15, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Nippon Raval
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Publication number: 20230244623Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window.Type: ApplicationFiled: December 8, 2021Publication date: August 3, 2023Applicant: ATI Technologies ULCInventors: Michael E. McLean, Philip Ng
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Patent number: 11714766Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).Type: GrantFiled: December 29, 2020Date of Patent: August 1, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Vinay Patel
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Publication number: 20230229603Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.Type: ApplicationFiled: December 30, 2021Publication date: July 20, 2023Inventors: PHILIP NG, NIPPON RAVAL, DAVID A. KAPLAN, DONALD P. MATTHEWS, JR.
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Patent number: 11698860Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.Type: GrantFiled: December 28, 2020Date of Patent: July 11, 2023Assignee: ATI TECHNOLOGIES ULCInventors: Nippon Raval, Philip Ng, Rostislav S. Dobrin
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Publication number: 20230214346Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: NIPPON RAVAL, PHILIP NG, JAROSLAW MARCZEWSKI
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Publication number: 20230151691Abstract: An apparatus to assist in the raising or lowering of a roller shade. The apparatus comprises a grab plate secured or securable to a bottom bar and a wand that is releasably securable to the grab plate. The grab plate comprising a receiver to releasably receive an upper end of the wand such that when wand’s upper end is moved vertically upward the roller shade is retracted, and when the wand is moved vertically downwardly the roller shade is lowered. The receiver comprises a mating surface against which a flange on the upper end of the wand bears when the wand is moved vertically upward. The receiver further comprises a retainer into which a locking member on the upper end of the wand is seatable when the wand is moved vertically downward.Type: ApplicationFiled: November 8, 2022Publication date: May 18, 2023Applicant: ZMC Metal Coating Inc.Inventor: Philip NG
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Patent number: 11630715Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.Type: GrantFiled: December 22, 2020Date of Patent: April 18, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Buheng Xu
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Publication number: 20230078439Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.Type: ApplicationFiled: November 22, 2022Publication date: March 16, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: GUHAN KRISHNAN, Carl K. Wakeland, Saikishore Reddipalli, Philip Ng
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Patent number: 11567666Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.Type: GrantFiled: March 24, 2021Date of Patent: January 31, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Nippon Raval
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Patent number: 11550722Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
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Patent number: D1012552Type: GrantFiled: July 8, 2022Date of Patent: January 30, 2024Assignee: ZMC Metal Coating Inc.Inventor: Philip Ng
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Patent number: D1012553Type: GrantFiled: July 8, 2022Date of Patent: January 30, 2024Assignee: ZMC Metal Coating Inc.Inventor: Philip Ng