Patents by Inventor Philip Raymond Germann

Philip Raymond Germann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8519304
    Abstract: A method, apparatus, and structure are provided for implementing selective rework for chip stacks. A backside metal layer to create resistive heating is added to a chip backside in a chip stack. A rework tool applies a predefined current to the backside metal layer to reflow solder connections and enables separating selected chips in the chip stack.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Philip Raymond Germann, Andrew Benson Maki
  • Patent number: 8174103
    Abstract: A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Patent number: 8108647
    Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson
  • Publication number: 20120006803
    Abstract: A method, apparatus, and structure are provided for implementing selective rework for chip stacks. A backside metal layer to create resistive heating is added to a chip backside in a chip stack. A rework tool applies a predefined current to the backside metal layer to reflow solder connections and enables separating selected chips in the chip stack.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Keith Bartley, Darryl John Becker, Philip Raymond Germann, Andrew Benson Maki
  • Patent number: 8079134
    Abstract: A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Andrew Benson Maki, Gerald Keith Bartley, Philip Raymond Germann, Mark Owen Maxson, Darryl John Becker, Paul Eric Dahlen, John Edward Sheets, II
  • Patent number: 8037270
    Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
  • Patent number: 8037272
    Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
  • Patent number: 8037258
    Abstract: A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
  • Patent number: 8019949
    Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann
  • Patent number: 7996641
    Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
  • Patent number: 7954081
    Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Trevor Joseph Timpane
  • Patent number: 7945883
    Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Patent number: 7921264
    Abstract: A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann
  • Patent number: 7921271
    Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann
  • Patent number: 7882479
    Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis
  • Patent number: 7852103
    Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Dennis Martin Rickert
  • Patent number: 7844769
    Abstract: A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Publication number: 20100271046
    Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Dennis Martin Rickert
  • Patent number: 7822936
    Abstract: A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann
  • Patent number: 7818512
    Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in a hierarchical tree configuration, in which at least some communications from an external source traverse successive levels of the tree to reach memory modules at the lowest level. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a tree configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann