Abstract: A method and system for providing a match on a selected event in performance monitoring of a processing system, the processing system including at least one performance monitor counter (PMC) is disclosed. The method and system comprises initializing the at least one PMC and controlling counting in the at least one PMC based upon the nth occurrence of a match to a specified address, where n is grater than or equal to one.

Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Abstract: An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: Data stream touch instructions are software-directed asynchronous prefetch instructions that can improve the performance of a system. Ideally, such instructions are used in perfect synchronization with the actual memory fetches that are trying to speed up. In practical situations, it is difficult to predict ahead of time all side effects of these instructions and memory access latency/throughput during execution of any large program. Incorrect usage of such instructions can cause degraded performance of the system. Thus, it is advantageous to measure the performance of such instructions.

Abstract: An apparatus for compare and maximum/minimum and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an a pair of vector operands and “true” and “false” comparison value signals for the corresponding operand data type. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract: Current software technology entails writing application programs in a high level language intended to facilitate portability to different computer processor platforms. Because the program is portable, the resulting object code is not tailored to run as efficiently as possible on the particular computer processor platform. Manually tuning a specific application program may be done, but it is time consuming and is rarely done by the end user. The disclosed invention provides an automated method of tuning application programs to execute more efficiently.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A vector pack instruction with saturation detection, for example, may be performed with one cycle latency by the crossbar and a correction multiplexer for substituting saturated values. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract: Current software technology entails writing application programs in a high level language intended to facilitate portability to different computer processor platforms. Because the program is portable, the resulting object code is not tailored to run as efficiently as possible on the particular computer processor platform. Manually tuning a specific application program may be done, but it is time consuming and is rarely done by the end user. The disclosed invention provides an automated method of tuning application programs to execute more efficiently.

Abstract: A multimedia facility within a processor employs a crossbar to perform operations requiring byte reordering. Prior to the cycle in which an instruction is executed, the instruction is checked to determine if the instruction is a predetermined type of instruction. If not, the operand which should contain encoded crossbar selects is filled with zeros before presentation to the crossbar select generation logic. If the instruction is one of the predetermined type of instructions, however, the real operand containing the encoded crossbar selects is presented to the crossbar select generation logic. As a result, only crossbar selects which designate byte 0 of the source operand as the source need to be qualified with a signal verifying the instruction being executed. The fanout of the qualification signal is thus reduced to an acceptable level, at which 1 cycle latency and 1 cycle throughput may be achieved.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.

Abstract: The present invention provides a performance monitor including a threshold indicator, a granularity indicator, an event detector, and an event counter. The threshold indicator indicates a number of threshold increments, which each correspond to a number of occurrences of a first event. The granularity indicator indicates the number of occurrences of the first event corresponding to each of the threshold increments indicated by the threshold indicator. The granularity indicator has at least a first state and a second state such that the granularity indicator indicates that a first number of occurrences of the first event correspond to a threshold increment in the first state and that a different second number of occurrences of the first event correspond to a threshold increment in the second state.

Abstract: A processor and method for tracking instruction execution within a processor are described. The processor includes at least one execution unit that executes instructions and an instruction status indicator that dynamically indicates a status of an instruction during processing. The instruction status indicator has at least a first state to which the instruction status indicator is set in order to indicate that execution of the instruction is stalled. In one embodiment, the processor further includes a reason code indicator associated with the instruction status indicator that specifies an event occurrence that caused the indicated instruction status. In another embodiment, the processor further includes a history buffer that indicates the number of processor cycles that the status indicated by the instruction status indicator has remained unchanged.

Abstract: Performance monitoring capabilities are expanded to an entire data processing system so that performance analyses can be made for operations occurring within the entire data processing system and not merely within the processor or any other device containing the performance monitor. Therefore, there is a provision for communicating performance monitor-related signals between the various performance monitors within the various devices and processor within a data processing system.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A method and system for identifying frequency and length of time of execution of serialization instructions in a pipeline of a processing system, the processing including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least PMCs, includes counting a number of instructions forcing serialization or logically requiring serialization of the pipeline during a predetermined sampling period. Further included are counting a number of additional cycles required to complete the instructions during the predetermined sampling period, and determining a loss of efficiency from the counted number of instructions and the counted number of additional cycles accumulated during the predetermined sampling period.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.