Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A method and system for performing performance monitoring within a data processing system whereby a counting function to be performed by a particular counter within the performance monitor is dependent upon a particular event programmed within another counter within the performance monitor so that reprogramming of all code points for each performance counter is not required.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A method and system for identifying inhibited interrupts in a processor system, the processor system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes initializing the at least one PMC and counting a number of cycles or occurrences with the at least one PMC that exceptions are ignored during a predetermined sampling period. In a second aspect the method and system provides for initializing at least one PMC and counting a number of cycles or occurrences with the at least one PMC that an interrupt is pending during the predetermined sampling period. The counted number of cycles/occurrences assists in identifying potential areas of improving system performance in order to reduce the counted values.

Abstract: A method for identifying bottlenecks within a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes, for a predetermined sampling period, counting a number of cycles that a dispatch unit is stalled, counting a number of cycles that each of a plurality of execution units is stalled, counting a number of cycles that a load/store unit is stalled, and counting a number of cycles that a completion unit is stalled. The counting in the units is performed to identify the relative effect of stalls occurring within each unit during processing to produce an overview of relative effect of the stalling of each unit on the total system bottleneck conditions.

Abstract: A method and system for monitoring performance of a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes identifying misaligned data items, and determining a performance penalty of misaligned data accesses during a predetermined sampling period.

Abstract: A method and system for determining the effectiveness of operation of a branch of a branch unit in a processing system the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one of the PMC, includes accumulating count data during branch unit operation with the at least one during a predetermined sampling period, and determining effectiveness of branch prediction based on the accumulated count data.

Abstract: A method and system for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period, counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period, and determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.

Abstract: A method of carburizing steel comprising carburizing steel under vacuum utilizing as the carburizing gas an aliphatic alcohol having 1 to 4 carbon atoms, preferably methanol and natural gas additions.