Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices.

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit.

Abstract: A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.

Abstract: A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.

Abstract: A link system controller is interposed between a PCI bus and the CPU data bus and memory data bus of a personal computer system to ensure that the transfer of data from the PCI bus to the CPU data bus occurs on different clock signals from the transfer of data from the PCI bus to the memory data bus. This is accomplished by an authorizing circuit, which alternately enables a CPU bus interface controller and a memory data bus controller in response to alternating clock signals. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise below an acceptable threshold; so that the operation of the IC system device is not impaired.

Abstract: A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

Abstract: The present invention relates to a system and method which has automatic enabling and disabling capabilities for prefetching and transferring sequentially located data from system memory to a First In First Out (FIFO) queue. When a Peripheral Component Interconnect (PCI) initiator signals for a data read, a minimum unit of data will be transferred from system memory to the FIFO queue. Only after seeing a certain number of consecutive data read requests from the same PCI initiator will the system begin to sequentially prefetch data from system memory and to transfer the prefetched data to the FIFO queue.