Link system controller interface linking a PCI bus to multiple other buses

- VLSI Technology, Inc.

A link system controller is interposed between a PCI bus and the CPU data bus and memory data bus of a personal computer system to ensure that the transfer of data from the PCI bus to the CPU data bus occurs on different clock signals from the transfer of data from the PCI bus to the memory data bus. This is accomplished by an authorizing circuit, which alternately enables a CPU bus interface controller and a memory data bus controller in response to alternating clock signals. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise below an acceptable threshold; so that the operation of the IC system device is not impaired.

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Claims

1. A link system controller in a computer system for controlling the transfer of data from a PCI bus to a CPU data bus and a memory data bus including in combination:

first and second buffers each having a data input coupled with a PCI bus, an enable input for controlling passage of data therethrough, and a data output, with the data output of said first buffer coupled with a CPU data bus, and the data output of said second buffer coupled with a memory data bus;
a CPU bus interface controller having an output connected with the enable input of said first buffer;
a memory bus controller having an output coupled with the enable input of said second buffer;
an authorizing switch circuit having a clock input and first and second outputs coupled with said CPU bus interface controller and said memory data bus controller, respectively, for alternately enabling said CPU bus interface controller and said memory data bus controller in response to clock signals supplied to the clock input of said authorizing switch circuit;
a source of clock signals connected with the clock input of said authorizing switch circuit and said CPU bus interface controller and said memory data bus controller for synchronizing the operation of said controllers and said authorizing switch circuit; and
said authorizing switch circuit enabling said CPU bus interface controller for supplying enable signals on the output thereof connected with said first buffer on first predetermined clock signals and enabling said memory data bus controller on second predetermined clock signals different from said first predetermined clock signals to supply enable signals on the output thereof connected with the enable input of said second buffer; so that said first and second buffers are enabled in synchronism with different clock signals to offset the initiation of the transfer of write data signals to said CPU data bus and said memory data bus.

2. The combination according to claim 1 wherein said first and second predetermined clock signals are alternating clock signals.

3. The combination according to claim 2 wherein said enable signals from said CPU bus interface controller and said memory data bus controller have a duration of a predetermined number of clock signals.

4. The combination according to claim 3 further including a third multi-stage buffer connected between said PCI bus and the data input of said first buffer and a fourth multi-stage buffer connected between the output of said first buffer and the data input of said second buffer.

5. The combination according to claim 4 wherein said third multi-stage buffer is coupled with said CPU bus interface controller and said fourth multi-stage buffer is coupled with said memory data bus controller for providing signals to said controllers indicative of the status of data in said third and fourth buffers, respectively, for initiating an enable signal output on the output of said CPU bus interface controller and for initiating an output signal from said memory data bus controller on the output thereof connected with the enable input of said second buffer.

6. The combination according to claim 1 wherein said enable signals from said CPU bus interface controller and said memory data bus controller have a duration of a predetermined number of clock signals.

7. The combination according to claim 1 further including a third multi-stage buffer connected between said PCI bus and the data input of said first buffer and a fourth multi-stage buffer connected between the output of said first buffer and the data input of said second buffer.

8. The combination according to claim 7 wherein said third multi-stage buffer is coupled with said CPU bus interface controller and said fourth multi-stage buffer is coupled with said memory data bus controller for providing signals to said controllers indicative of the status of data in said third and fourth buffers, respectively, for initiating an enable signal output on the output of said CPU bus interface controller and for initiating an output signal from said memory data bus controller on the output thereof connected with the enable input of said second buffer.

Referenced Cited
U.S. Patent Documents
4669044 May 26, 1987 Houser et al.
5038276 August 6, 1991 Bozzetti et al.
5333301 July 26, 1994 Cheney et al.
5483642 January 9, 1996 Okazawa et al.
5553265 September 3, 1996 Abato et al.
5557758 September 17, 1996 Bland et al.
5574921 November 12, 1996 Curran
5621902 April 15, 1997 Cases et al.
Patent History
Patent number: 5737544
Type: Grant
Filed: Apr 8, 1996
Date of Patent: Apr 7, 1998
Assignee: VLSI Technology, Inc. (San Jose, CA)
Inventor: Philip Wszolek (Phoenix, AZ)
Primary Examiner: Ayaz R. Sheikh
Assistant Examiner: David A. Wiley
Attorney: LaValle D. Ptak
Application Number: 8/628,969
Classifications
Current U.S. Class: 395/287
International Classification: G06F 1300;