Patents by Inventor Philipp Riess
Philipp Riess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11201151Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.Type: GrantFiled: March 27, 2020Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Richard Hudeczek, Philipp Riess, Richard Geiger, Peter Baumgartner
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Publication number: 20210305245Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Richard HUDECZEK, Philipp RIESS, Richard GEIGER, Peter BAUMGARTNER
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Patent number: 11024712Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.Type: GrantFiled: June 27, 2018Date of Patent: June 1, 2021Assignee: Intel IP CorporationInventors: Vase Jovanov, Peter Baumgartner, Gregor Bracher, Luis Giles, Uwe Hodel, Andreas Lachmann, Philipp Riess, Karl-Henrik Ryden
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Publication number: 20200006483Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: Vase JOVANOV, Peter BAUMGARTNER, Gregor BRACHER, Luis GILES, Uwe HODEL, Andreas LACHMANN, Philipp RIESS, Karl-Henrik RYDEN
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Patent number: 9793220Abstract: A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.Type: GrantFiled: December 28, 2012Date of Patent: October 17, 2017Assignee: INTEL DEUTSCHLAND GMBHInventors: Hans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
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Patent number: 9385105Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.Type: GrantFiled: January 10, 2013Date of Patent: July 5, 2016Assignee: Intel Deutschland GmbHInventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas, Hans-Joachim Barth, Sven Albers, Reinhard Golly, Philipp Riess, Bernd Ebersberger
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Publication number: 20150084196Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: ApplicationFiled: October 6, 2014Publication date: March 26, 2015Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Publication number: 20150028478Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.Type: ApplicationFiled: January 10, 2013Publication date: January 29, 2015Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas, Hans-Joachim Barth, Sven Albers, Reinhard Golly, Philipp Riess, Bernd Ebersberger
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Patent number: 8901624Abstract: In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.Type: GrantFiled: July 26, 2013Date of Patent: December 2, 2014Assignee: Infineon Technologies AGInventors: Philipp Riess, Domagoj Siprak
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Patent number: 8860225Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: GrantFiled: October 12, 2011Date of Patent: October 14, 2014Assignee: Infineon Technologies AGInventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Patent number: 8710590Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.Type: GrantFiled: June 16, 2006Date of Patent: April 29, 2014Assignee: Infineon Technologies AGInventors: Philipp Riess, Henning Feick, Martin Wendel
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Publication number: 20130307091Abstract: In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.Type: ApplicationFiled: July 26, 2013Publication date: November 21, 2013Inventors: Philipp Riess, Domagoj Siprak
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Patent number: 8569820Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: GrantFiled: January 6, 2012Date of Patent: October 29, 2013Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Publication number: 20130240884Abstract: A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.Type: ApplicationFiled: December 28, 2012Publication date: September 19, 2013Applicant: Intel Mobile Communications GmbHInventors: Hans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
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Patent number: 8536677Abstract: One or more embodiments relate to a capacitor structure comprising a first and second capacitor electrode. The first electrode may include a conductive strip having at least one wider portion and at least one narrower portion. The second electrode may include a conductive strip having at least one wider portion and at least one narrower portion.Type: GrantFiled: September 19, 2008Date of Patent: September 17, 2013Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Philipp Riess
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Patent number: 8518811Abstract: In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.Type: GrantFiled: April 8, 2011Date of Patent: August 27, 2013Assignee: Infineon Technologies AGInventors: Philipp Riess, Domagoj Siprak
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Patent number: 8508019Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.Type: GrantFiled: July 5, 2012Date of Patent: August 13, 2013Assignee: Infineon Techn. AGInventor: Philipp Riess
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Patent number: 8394696Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.Type: GrantFiled: December 17, 2010Date of Patent: March 12, 2013Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Philipp Riess, Thomas Benetik
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Patent number: 8314452Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.Type: GrantFiled: December 22, 2011Date of Patent: November 20, 2012Assignee: Infineon Technologies AGInventors: Philipp Riess, Armin Fischer
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Publication number: 20120267762Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.Type: ApplicationFiled: July 5, 2012Publication date: October 25, 2012Inventor: Philipp RIESS