Patents by Inventor Philipp Riess
Philipp Riess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120256274Abstract: In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Inventors: Philipp Riess, Domagoj Siprak
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Patent number: 8242579Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.Type: GrantFiled: May 25, 2009Date of Patent: August 14, 2012Assignee: Infineon Technologies AGInventor: Philipp Riess
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Publication number: 20120099243Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: ApplicationFiled: January 6, 2012Publication date: April 26, 2012Applicant: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Publication number: 20120091560Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.Type: ApplicationFiled: December 22, 2011Publication date: April 19, 2012Applicant: Infineon Techonlogies AGInventors: Philipp Riess, Armin Fischer
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Patent number: 8138539Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: GrantFiled: November 29, 2007Date of Patent: March 20, 2012Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Publication number: 20120025382Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: ApplicationFiled: October 12, 2011Publication date: February 2, 2012Applicant: Infineon Technologies AGInventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Patent number: 8101495Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.Type: GrantFiled: March 13, 2008Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: Philipp Riess, Armin Fischer
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Patent number: 8062971Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: GrantFiled: March 19, 2008Date of Patent: November 22, 2011Assignee: Infineon Technologies AGInventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Publication number: 20110086487Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.Type: ApplicationFiled: December 17, 2010Publication date: April 14, 2011Inventors: Peter Baumgartner, Philipp Riess, Thomas Benetik
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Patent number: 7906831Abstract: One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil.Type: GrantFiled: September 23, 2008Date of Patent: March 15, 2011Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Philipp Riess
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Publication number: 20100295154Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.Type: ApplicationFiled: May 25, 2009Publication date: November 25, 2010Inventor: Philipp RIESS
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Publication number: 20100072572Abstract: One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil.Type: ApplicationFiled: September 23, 2008Publication date: March 25, 2010Inventors: Peter BAUMGARTNER, Philipp RIESS
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Publication number: 20090239375Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Publication number: 20090230507Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.Type: ApplicationFiled: March 13, 2008Publication date: September 17, 2009Inventors: Philipp Riess, Armin Fischer
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Publication number: 20090141424Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Patent number: 7485945Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.Type: GrantFiled: October 3, 2006Date of Patent: February 3, 2009Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Philipp Riess, Thomas Benetik, Dieter Draxelmayr
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Publication number: 20090014832Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.Type: ApplicationFiled: July 9, 2007Publication date: January 15, 2009Inventors: Peter Baumgartner, Philipp Riess, Thomas Benetik
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Publication number: 20090009926Abstract: One or more embodiments relate to a capacitor structure comprising a first and second capacitor electrode. The first electrode may include a conductive strip having at least one wider portion and at least one narrower portion. The second electrode may include a conductive strip having at least one wider portion and at least one narrower portion.Type: ApplicationFiled: September 19, 2008Publication date: January 8, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Peter BAUMGARTNER, Philipp RIESS
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Publication number: 20070181924Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.Type: ApplicationFiled: October 3, 2006Publication date: August 9, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Baumgartner, Philipp Riess, Thomas Benetik, Dieter Draxelmayr
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Publication number: 20070010077Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.Type: ApplicationFiled: June 16, 2006Publication date: January 11, 2007Inventors: Philipp Riess, Henning Feick, Martin Wendel