Abstract: A system and method is disclosed for multiple chips in which the connection between chips is made with registered inputs and registered outputs. This is achieved using a credit-based flow control protocol between the chips. The connection is made as part of a single packet-based on-chip and between-chip network with a common address space between the two chips.

Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract: The system of interconnections (20) for external functional blocks on a chip provided with a single configurable communication protocol, comprises two physically separate communication networks (21, 22): a request network (21) for transmitting request messages from an initiating block (23, 24, 25, 26) to a recipient block (27, 28, 29, 30, 31) and a response network (22) for transmitting response messages from a recipient block (27, 28, 29, 30, 31) to an initiating block (23, 25, 26). The response messages include additional information making said request (21) and response (22) networks able to respectively manage the request messages and the response messages independently.

Abstract: A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.

Abstract: A system and method is disclosed for multiple chips in which the connection between chips is made with registered inputs and registered outputs. This is achieved using a credit-based flow control protocol between the chips. The connection is made as part of a single packet-based on-chip and between-chip network with a common address space between the two chips.

Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.

Abstract: A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.

Abstract: An asynchronous clock adapter is disclosed that transmits multiple data elements from a buffer in a source clock domain to a data register in a destination clock domain. The buffer can be selected by a pointer register in the destination clock domain and a round trip timing path exists from the pointer register to the data register. Data elements from the buffer can be sent on interleaved cycles of the destination clock such that each data element can have a delay constraint of more than one clock period.

Abstract: A probe within a Network-on-Chip (NoC) that can calculate a histogram of transaction data is disclosed. Some such histograms are cycles per number of pending transactions, transactions per latency, and transactions per request delay. The number of pending transactions can be measured by a register that is incremented at the start and decremented at the end of each transaction. Latencies can be measured by timers that are allocated and initialized at the start and read at the end of each transaction. Multiple counters can be used for multiple pending transactions. Multiple banks of counters can be used so that multiple transaction interfaces can complete transactions and perform histogram bin threshold comparisons simultaneously. The thresholds separating histogram bins can be programmable.

Abstract: Quality-of-Servitrce (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).

Abstract: Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time.

Abstract: The system for managing messages transmitted in an interconnect network connecting blocks on a chip comprises agents linked by point-to-point links able to transmit, by static routing, messages comprising a priority information item quantified on N levels. The system comprises at least one agent initiating request messages to at least one recipient agent. A request message comprises a header and, where appropriate, content data. The system comprises means of generating a priority message, to a recipient agent, to which at least on request message has previously been transmitted with no response message received in return.