Abstract: Quality-of-Service (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).

Abstract: Method for transmitting a sequence of messages in a point-to-point interconnection network comprising message initiating agents, message destination agents and message transmission agents. During a transmission of an indivisible sequence of messages from an initiating agent to a destination agent, an output of a message transmission agent is locked onto an input of the transmission agent, the other inputs of the said transmission agent being able to transmit messages to the other outputs of the said transmission agent.

Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.

Abstract: In some embodiments, a system for communication between agents in a point-to-point interconnection system includes at least one initiator agent capable of dispatching at least one message destined for at least one determined receiver agent; at least one intermediate agent capable of forwarding at least one message to at least one determined receiver agent; at least one receiver agent capable of receiving at least one message originating from an initiator agent via at least one intermediate agent; and means of error detection and means of erroneous message marking. In some embodiments, a receiver agent includes means for formulating an error message and means for sending the error message to the initiator agent so as to warn the said initiator agent of the presence of an error.

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract: The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs.

Abstract: The message switching system (51) comprises at least two inputs (52, 53, 54, 55) and at least one output (56), first arbitration means (62) dedicated to said output (56), and management means (64) designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system (51) and having sent requests for the assignment of said output (56), and designed to assign said output (56). Said management means (64) comprise storage means (70) designed to store said relative orders OR(i,j), initialization means (66) designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means (68) designed to update all of said relative orders when a new request arrives at said first arbitration means (62), or when said output is assigned to one of said inputs.

Abstract: In some embodiments, a system for communication between agents in a point-to-point interconnection system includes at least one initiator agent capable of dispatching at least one message destined for at least one determined receiver agent; at least one intermediate agent capable of forwarding at least one message to at least one determined receiver agent; at least one receiver agent capable of receiving at least one message originating from an initiator agent via at least one intermediate agent; and means of error detection and means of erroneous message marking. In some embodiments, a receiver agent includes means for formulating an error message and means for sending the error message to the initiator agent so as to warn the said initiator agent of the presence of an error.

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract: This system for determining the performance of an interconnection network of functional blocks of a specialized integrated circuit, comprises a set of probing modules disposed on the network and comprising means for detecting an event on at least one communication link of the network and means for determining a characteristic indicative of the activity of the said at least one link on the basis of the detection of the said event.

Abstract: Method for managing messages transmitted in an on-chip interconnect network (3), in which a sender agent (6) sends a message requesting available processing capacity (Req_writing_1(N data)) destined for a receiver agent (8), the said message requesting capacity (Req_writing_1(N data)) comprising the destination address of the receiver agent (8) and being of size less than or equal to a predetermined size, sends an instruction message (Dispatch_of_N_data) when the receiver agent (8) is ready to process the said instructions, and releases all or part of the memory space occupied by the said instruction message (Dispatch_of_N_data) after the said sending of the said stored instruction message (Dispatch_of_N_data).

Abstract: The system for managing messages transmitted in an interconnect network connecting blocks on a chip comprises agents linked by point-to-point links able to transmit, by static routing, messages comprising a priority information item quantified on N levels. The system comprises at least one agent (1) initiating request messages to at least one recipient agent (2). A request message comprises a header and, where appropriate, content data. The system comprises means (5) of generating a priority message, to a recipient agent (2), to which at least one request message has previously been transmitted with no response message received in return.

Abstract: The message switching system (51) comprises at least two inputs (52, 53, 54, 55) and at least one output (56), first arbitration means (62) dedicated to said output (56), and management means (64) designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system (51) and having sent requests for the assignment of said output (56), and designed to assign said output (56). Said management means (64) comprise storage means (70) designed to store said relative orders OR(i,j), initialization means (66) designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means (68) designed to update all of said relative orders when a new request arrives at said first arbitration means (62), or when said output is assigned to one of said inputs.

Abstract: System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol The system of interconnections (20) for external functional blocks on a chip provided with a single configurable communication protocol, comprises two physically separate communication networks (21, 22): a request network (21) for transmitting request messages from an initiating block (23, 24, 25, 26) to a recipient block (27, 28, 29, 30, 31) and a response network (22) for transmitting response messages from a recipient block (27, 28, 29, 30, 31) to an initiating block (23, 25, 26). The response messages include additional information making said request (21) and response (22) networks able to respectively manage the request messages and the response messages independently.

Abstract: The system for the static routing of streams of data packets in an interconnect network comprises: at least one sending element (2), one receiving element (3), and one link set (4) of unidirectional communication links linking said sending element (2) to said receiving element (3), means (9) of detecting a stream identifier of a data packet, and dynamic routing management means (8), designed to keep the order of output of the data packets of one and the same stream from said receiving element (3) identical to the order of arrival of said packets at said sending element (2).

Abstract: The system for on-circuit asynchronous communication, between synchronous subcircuits, includes a first synchronous subcircuit regulated by a first clock frequency, which sends requests to a second synchronous subcircut regulated by a second clock frequency. The first subcircuit transmits data to the second subcircuit through a first mesochronous unidirectional communication link, and the second subcircuit transmits availability tokens which report the availability of an additional elementary memory location in the queue situated at the extremity of the first mesochronous unidirectional communication link to the first subcircuit, via a second mesochronous unidirectional communication link. The first subcircuit comprises means of transmission for directly transmitting to the second subcircuit data of a size that is at most equal to the size corresponding to the elementary memory locations available in the queue.

Abstract: Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.

Abstract: In some embodiments, a system for communication between agents in a point-to-point interconnection system includes at least one initiator agent capable of dispatching at least one message destined for at least one determined receiver agent; at least one intermediate agent capable of forwarding at least one message to at least one determined receiver agent; at least one receiver agent capable of receiving at least one message originating from an initiator agent via at least one intermediate agent; and means of error detection and means of erroneous message marking. In some embodiments, a receiver agent includes means for formulating an error message and means for sending the error message to the initiator agent so as to warn the said initiator agent of the presence of an error.