Abstract: A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract: A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.

Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Abstract: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells.

Abstract: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.

Abstract: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18?, 20?) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18?).

Abstract: A memory cell of the SRAM type Is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).