Patents by Inventor Philippe Galy

Philippe Galy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10659034
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Renan Lethiecq
  • Publication number: 20200119024
    Abstract: A method can be used to irreversibly program a memory cell that includes a MOS transistor having a first source/drain region and a second source/drain region separated by a channel region that is adjacent a gate region. The method includes applying an electric current along a width of the first source/drain region to cause a resistivity of the first source/drain region to be irreversibly increased.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Inventors: Philippe Galy, Renan Lethiecq
  • Patent number: 10607949
    Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 31, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Yves Mazoyer, Philippe Galy, Philippe Sirito-Olivier
  • Publication number: 20200097036
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 26, 2020
    Applicant: STMicroelectronics SA
    Inventors: Renan LETHIECQ, Philippe GALY
  • Publication number: 20200013901
    Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Publication number: 20200006320
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Louise DE CONTI, Philippe GALY
  • Publication number: 20190372568
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • Publication number: 20190288079
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Sotirios ATHANASIOU, Philippe GALY
  • Patent number: 10367068
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics SAA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Publication number: 20190181131
    Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • Publication number: 20190164973
    Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 30, 2019
    Applicant: STMicroelectronics SA
    Inventors: Hassan EL DIRANI, Thomas BEDECARRATS, Philippe GALY
  • Publication number: 20190114145
    Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 18, 2019
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Patent number: 10211201
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Publication number: 20180351353
    Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Yves Mazoyer, Philippe Galy, Philippe Sirito-Olivier
  • Patent number: 10128242
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 10096708
    Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 9, 2018
    Assignee: STMicroelectronics SA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Publication number: 20180276536
    Abstract: An integrated artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after delivery of an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to the output node by a second MOS transistor having a first electrode coupled to the supply node and a gate coupled to the output node. The refractory circuit further includes a resistive-capacitive circuit coupled between the supply node, the reference node and the gate of the second MOS transistor. An inhibition duration depends on a time constant of the resistive-capacitive circuit.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 27, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Publication number: 20180276526
    Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Publication number: 20180197848
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 9991173
    Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate, thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: June 5, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Johan Bourgeat