Patents by Inventor Philippe Galy

Philippe Galy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210278287
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • Publication number: 20210278286
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • Publication number: 20210278288
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • Patent number: 11037938
    Abstract: An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 15, 2021
    Assignee: STMICROELECTRONICS S.A.
    Inventors: Philippe Galy, Renan Lethiecq
  • Publication number: 20210020660
    Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 21, 2021
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Philippe GALY
  • Publication number: 20210020663
    Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 21, 2021
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Thomas BEDECARRATS
  • Patent number: 10853038
    Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 1, 2020
    Assignee: STMICROELECTRONICS SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Publication number: 20200373965
    Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 26, 2020
    Applicant: STMicroelectronics SA
    Inventors: Mohammed TMIMI, Philippe GALY
  • Publication number: 20200357788
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise DE CONTI, Philippe GALY
  • Publication number: 20200357902
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • Patent number: 10804275
    Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Hassan El Dirani, Thomas Bedecarrats, Philippe Galy
  • Patent number: 10795396
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics SA
    Inventors: Renan Lethiecq, Philippe Galy
  • Patent number: 10659034
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Renan Lethiecq
  • Publication number: 20200119024
    Abstract: A method can be used to irreversibly program a memory cell that includes a MOS transistor having a first source/drain region and a second source/drain region separated by a channel region that is adjacent a gate region. The method includes applying an electric current along a width of the first source/drain region to cause a resistivity of the first source/drain region to be irreversibly increased.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Inventors: Philippe Galy, Renan Lethiecq
  • Patent number: 10607949
    Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 31, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Yves Mazoyer, Philippe Galy, Philippe Sirito-Olivier
  • Publication number: 20200097036
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 26, 2020
    Applicant: STMicroelectronics SA
    Inventors: Renan LETHIECQ, Philippe GALY
  • Publication number: 20200013901
    Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Publication number: 20200006320
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Louise DE CONTI, Philippe GALY
  • Publication number: 20190372568
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • Publication number: 20190288079
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Sotirios ATHANASIOU, Philippe GALY