Abstract: An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.

Abstract: An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

Abstract: An electrostatic discharge protection circuit incudes an electrostatic discharge dissipation component having a first conduction terminal, a second conduction terminal, and a control terminal. Identical first and second devices each include first and second conduction terminals, where the respective first conduction terminals of the first and second devices are connected to the control terminal of the electrostatic discharge dissipation component, and the respective second terminals of the first and second devices are respectively connected to the first conduction terminal of the electrostatic discharge dissipation component and to the second conduction terminal of the electrostatic discharge dissipation component.

Abstract: An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.

Abstract: An electrostatic discharge protection device is formed using only electrically connected transistors. The transistors include: a first MOS-type transistor forming a clamping circuit coupled between first and second supply nodes; a second MOS-type transistor coupled between the first supply node and a gate terminal of the first MOS-type transistor; and a third MOS-type transistor having a first gate terminal coupled to a gate terminal of the second MOS-type transistor, a second gate terminal coupled to one of the first and second supply nodes, and first and second conduction terminals coupled to the second supply node.

Abstract: A set of spike pattern data is stored on a set of storage neurons of a neural network. The storing includes storing first parameters indicative of a presence of spikes on respective neurons of the set of storage neurons, and storing, on the set of storage neurons of the neural network, second parameters indicative of a timing of spikes on the respective neurons of the set of storage neurons.

Abstract: A neural network circuit having at least one first neuron coupled to a second neuron via at least one synapse. A non-linear current attenuator receives a first current from the at least one synapse and provides a second current to the second neuron.

Abstract: A method includes generating, by a first spiking neuron, an event detection signal indicating a time of detection of an event in a data flow. The event detection signal is transmitted from the first spiking neuron to a second spiking neuron. The second spiking neuron generates a spike delayed, with respect to the time of detection of the event, according to an amplitude of the event. The delayed spike is included in a coded signal.

Abstract: An electronic component includes a gate structure over a semiconductor layer. The gate structure is insulated from the semiconductor layer and includes a layer made of a magnetic material. The electronic component may form a FET transistor, a MOSFET transistor, a SET transistor, a gated diode, a gated MOS structure, or a gated quantum dot.

Abstract: An electrostatic discharge protection circuit protects a first transistor. The circuit includes N diodes in series between conduction terminals of the first transistor. A second transistor and third transistor are connected in series between the conduction terminals of the first transistor. A control terminal of the third transistor is coupled to an anode of the N diodes. A first inverter couples the control terminals of the first and second transistors. A fourth transistor is connected in parallel with the first transistor. A control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. A capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.

Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

Abstract: A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.

Abstract: An electrostatic discharge protection device is formed using only electrically connected transistors. The transistors include: a first MOS-type transistor forming a clamping circuit coupled between first and second supply nodes; a second MOS-type transistor coupled between the first supply node and a gate terminal of the first MOS-type transistor; and a third MOS-type transistor having a first gate terminal coupled to a gate terminal of the second MOS-type transistor, a second gate terminal coupled to one of the first and second supply nodes, and first and second conduction terminals coupled to the second supply node.

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

Abstract: An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.