Abstract: An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.

Abstract: Embodiments of circuitry, which includes an operational transconductance amplifier and a passive circuit, are disclosed. The passive circuit is coupled to the operational transconductance amplifier. Further, the passive circuit receives an input signal and the operational transconductance amplifier provides an output current, such that the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output signal.

Abstract: The present disclosure relates to an RF power amplifier (PA) power supply that includes a series pass circuit coupled across a direct current (DC)-to-DC converter to receive a power supply input signal, such as provided from a battery, to provide a power supply output signal to at least a first RF PA based on an output setpoint. Control circuitry selects between a switching supply operating mode and a non-switching supply operating mode based on the output setpoint. During the switching supply operating mode, the DC-to-DC converter provides the power supply output signal and during the non-switching supply operating mode, the series pass circuit provides the power supply output signal.

Abstract: Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a VRAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.

Abstract: The present disclosure provides a system and method for controlling positioning of a movable member of a MEMS microactuator to reduce bouncing and ringing. The system includes control circuitry in communication with the MEMS microactuator. The control circuitry is adapted to linearly increase an actuation signal from a first state to a second state to urge the movable member from a first position to a second position and hold the movable member in the second position. The control circuitry is further adapted to linearly decrease the actuation signal from the second state to the first state to release the movable member to the first position. A transition time is not less than the inverse of one quarter of a natural frequency of the movable member as the movable member moves to the first position.

Abstract: A high voltage charge-pump having a feedback control loop is disclosed. The high voltage charge-pump includes a plurality of voltage boosting stages, a low voltage input, and at least one clock input. A sensing charge-pump having a voltage detector output has at least one voltage sensing stage that is communicably coupled to at least one of the plurality of voltage boosting stages. A loop filter in the feedback control loop includes a voltage detector input coupled to the voltage detector output, a voltage reference input, and a voltage error output. A voltage controlled oscillator (VCO) with a variable frequency output has a voltage error input coupled to the voltage error output. The feedback control loop also includes at least one driver having a variable frequency input coupled to the variable frequency output and at least one clock output coupled to the at least one clock input.

Abstract: The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.

Abstract: A charge pump includes an input, an output, and a fixed voltage node; a first capacitor and at least a second capacitor; and a plurality of switches adapted to selectively couple the first capacitor and the at least the second capacitor to the input, the output, and the fixed voltage node. A switch controller is adapted to switch the plurality of switches in response to at least three phase signals to provide fixed gains. A phase generator is adapted to generate the at least three phase signals, wherein at least one of the at least three phase signals has a duty cycle that is different from at least one other of the at least three phase signals. The phase generator is also adapted to adjust the frequency of a clock signal used to generate the at least three phase signals so that a minimum switching frequency is provided.

Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.

Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.

Abstract: A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator arranged to provide a first-order quantized output and a feedback path output. A second order sigma-delta modulator is arranged to receive the feedback path output and provides a second order quantized output. A combination block combines the first and second order quantized outputs to provide a combined third order quantized output, which provides noise shaping with a frequency notch spectrum. In this way a new quantization noise shape of third order is provided, such that quantization phase noise may be lowered, the PLL loop bandwidth may be increased, modulation phase error may be reduced and PLL locking speed increased.

Abstract: A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator (500) arranged to provide a first-order quantized output and a feedback path output (508). A second order sigma-delta modulator (520) is arranged to receive the feedback path output (508) and provides a second order quantized output. A combination block (530) combines the first and second order quantized outputs to provide a combined third order quantized output (540), which provides noise shaping with a frequency notch spectrum. In this way a new quantization noise shape of third order is provided, such that quantization phase noise may be lowered, the PLL loop bandwidth may be increased, modulation phase error may be reduced and PLL locking speed increased.

Abstract: A multiplier (10) includes a transconductor (14) and a multiplier core (34). The transconductor (14) converts an RF voltage signal to an RF current signal. The RF current signal modulates the quiescent currents flowing in current conducting elements (23, 24), thereby generating a modulated current signal. The modulated current signal is transmitted to the multiplier core (34), where it is combined with an LO signal to generate an output signal. The transconductor (14) and the multiplier core (34) have their current conduction paths separated from each other by the current conducting elements (23, 24).

Abstract: A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.

Abstract: A programmable frequency divider circuit includes a prescaler which consists of p cascade-connected dividing cells, a cell of rank i in the cascade having a normal division factor 2 and also being programmable so as to divide by 3 the input frequency applied to the cell. Each cell of rank i supplies, as a signal enabling the programmed mode for the preceding cell of rank i-1, a signal which is referred to as a gating signal and which is calibrated as regards duration and position in time at the operating frequency of the cell i, the prescaler (PPSC) being associated with counting means (CNT) for producing a programmable division factor (R) which is equal to M.2.sup.p +N, where M is an integer number applied to the counting means (CNT), p is the number of cells of the prescaler (PPSC), and N is an integer number applied to the programming inputs of the prescaler (PPSC).