Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.

Abstract: Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps.

Abstract: Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps.

Abstract: Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps.

Abstract: A wheel includes a hub portion configured to rotate about a rotational axis. A plurality of blades extends radially outward from the hub portion. Each blade of the plurality of blades includes a leading edge and a trailing edge. The hub portion and the plurality of blades include a substrate metal. The substrate metal of the plurality of blades has coated directly thereon a coating layer that has a hardness of about 800 HV or greater and that includes electroless nickel-phosphorous having a phosphorous content of from about 2 to about 4 wt. %.

Abstract: The particle (1) is suitable for the manufacture of an implantable soft tissue engineering material and comprises a three-dimensionally warped and branched sheet (2) where: (i) the three-dimensionally warped and branched sheet (2) is made from a biocompatible material having a Young's modulus of 1 kPa to 1 GPa; (ii) the three-dimensionally warped and branched sheet (2) has an irregular shape which is encompassed in a virtual three-dimensional envelope (3) having a volume VE; (iii) the three-dimensionally warped and branched sheet (2) has a mean sheet thickness T; (iv) the three-dimensionally warped and branched sheet (2) has a volume VS; (v) the particle (1) has a Young's modulus of 100 Pa to 15 kPa; and (vi) the particle (1) further comprises a number of protrusions (4) where the three-dimensionally warped and branched sheet (2) reaches the envelope (3); (vii) the particle (1) has a number of interconnected channel-type conduits (5) defined by the branching of the sheet (2) and/or by voids in the sheet (2

Abstract: A method for determining the presence of a molecule coupled to the cytoplasmic side of a cellular membrane is disclosed. The method is implemented in a microfluidic setting and is particularly suitable for determining the presence and/or the activity of a G protein or an arrestin protein in a cell.

Abstract: A wheel includes a hub portion configured to rotate about a rotational axis. A plurality of blades extends radially outward from the hub portion. Each blade of the plurality of blades includes a leading edge and a trailing edge. The hub portion and the plurality of blades include a substrate metal. The substrate metal of the plurality of blades has coated directly thereon a coating layer that has a hardness of about 800 HV or greater and that includes electroless nickel-phosphorous having a phosphorous content of from about 2 to about 4 wt. %.

Abstract: A method includes forming a semiconductor device that includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.

Abstract: The invention provides for a steerable guidewire for insertion into a body cavity, characterized in that is comprises an elongated body defining a longitudinally-arranged lumen comprising i) a proximal end portion and ii) a distal end portion comprising a spatially reconfigurable portion and a tip; a pull wire located along said lumen and affixed to said distal end portion and to said proximal end; an actuation region located on said proximal end portion adapted to impart a tension force on the pull wire resulting in a compression force to the spatially reconfigurable region; and an intermediate region tubular element on said body located between said spatially reconfigurable portion and said proximal end.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode are formed over the semiconductor substrate. The first current-carrying electrode and the second current-carrying electrode include a first conductive layer formed within first openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate between the first current-carrying electrode and the second current-carrying electrode. A first conductive element that includes the first conductive layer is formed over the first dielectric layer, adjacent to the control electrode, and between the control electrode and the second current-carrying electrode.

Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a first dielectric layer over the passivation layer, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends through the passivation layer. The conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.

Abstract: A wheel includes a hub portion configured to rotate about a rotational axis. A plurality of blades extends radially outward from the hub portion. Each blade of the plurality of blades includes a leading edge and a trailing edge. The hub portion and the plurality of blades include a substrate metal. The substrate metal of the plurality of blades has coated directly thereon a coating layer that has a hardness of about 800 HV or greater and that includes electroless nickel-phosphorous having a phosphorous content of from about 2 to about 4 wt. %.

Abstract: A wheel includes a hub portion configured to rotate about a rotational axis. A plurality of blades extends radially outward from the hub portion. Each blade of the plurality of blades includes a leading edge and a trailing edge. The hub portion and the plurality of blades include a substrate metal that includes aluminum or an alloy thereof. The substrate metal of the plurality of blades has coated directly thereon a first coating layer including electroless nickel-phosphorous. The first coating layer has coated directly thereon a second hard coating layer that overlies the leading edges of the plurality of blades and that is formed of a physical vapor deposition-compatible material.

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

Abstract: The present invention generally belongs to the fields of medtech, labtech and impedance analysis. In particular, the present invention pertains methods and apparatuses for identification and isolation of biological entities such as cells trough impedance analyses.

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

Abstract: The invention is achieved by a volumetric displacement calibration device (1) configured to be able to adapt at least one suction system (1000), comprising a tip (1006), having a volume VP, connected to a shaft (1003) comprising a volume change mechanism (1002). The device (1) comprises at least one main chamber (10) and one reference chamber (20), connected by a conduct (100) and a valve (102) to said main chamber (10) and at least one first pressure sensor (12) connected to said main chamber (10). The device (1) comprises also a second pressure sensor (22) connected to said reference chamber (20). The pressure sensors and calculation means allow to calculate an internal volume Vo, being the sum of the volume VP of said aspiration tip (1006), the volume (1005) of the shaft (1003) when the volume change mechanism (1002) is down. The invention is also achieved by a system (2) comprising the device (1) and at least one suction system (10001-1000n) adapted to said device (1).

Abstract: A semiconductor device and method of manufacture is presented. A silicon-on-insulator (SOI) substrate includes a layer of gallium nitride on a first surface of the SOI substrate. A device is formed over the first surface of the substrate and a first conductive feature is formed over the first surface of the substrate and electrically coupling the first conductive feature to the device. A first cavity is formed in a second surface of the SOI substrate directly below the first conductive feature, wherein the first cavity includes first upper cavity surface defined by a surface of a layer of silicon dioxide in the SOI substrate.

Abstract: A wheel includes a hub portion configured to rotate about a rotational axis. A plurality of blades extends radially outward from the hub portion. Each blade of the plurality of blades includes a leading edge and a trailing edge. The hub portion and the plurality of blades include a substrate metal. The substrate metal of the plurality of blades has coated directly thereon a first coating layer including electroless nickel-phosphorous having a phosphorous content of about 4 wt. % or greater. The first coating layer has coated directly thereon overlying the plurality of blades a second coating layer including electroless nickel-phosphorous poly-alloy having a phosphorous content that is lower than the phosphorous content of the first coating layer. The second coating layer is a functional coating layer with enhanced erosion resistance.