Patents by Inventor Philippe Roche
Philippe Roche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299009Abstract: An electronic device includes a first electronic chip, a second electronic chip, and an interconnection circuit. A first region of a first surface of the first electronic chip is assembled by hybrid bonding to a third region of a third surface of the interconnection circuit. A second region of a second surface of the second electronic chip is assembled by hybrid to a fourth region of the third surface of the interconnection circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnection circuit. The first surface of the first electronic chip further includes a fifth region which is not in contact with the interconnection circuit. This fifth region includes a connection pad electrically connected by a connection element to a connection substrate to which the interconnection circuit is mounted.Type: ApplicationFiled: March 13, 2023Publication date: September 21, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Fady ABOUZEID, Philippe ROCHE
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Patent number: 11225481Abstract: This invention relates to xanthine derivative compounds that are inhibitors of BET bromodomains proteins, the method of preparation thereof and applications thereof.Type: GrantFiled: December 27, 2016Date of Patent: January 18, 2022Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INSTITUT NATIONAL DE LA SANTE ET DE LA RECHERCHE MEDICALE (INSERM), UNIVERSITÉ D'AIX-MARSEILLE, INSTITUT JEAN PAOLI & IRENE CALMETTESInventors: Xavier Morelli, Sébastien Combes, Jean-Claude Guillemot, Stéphanie Betzi, Yves Collette, Philippe Roche, Adrien Lugari, Sabine Milhas, Brigitt Raux, Iuliia Voitovich
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Patent number: 11180510Abstract: The present invention relates to a compound having the following formula (I): (I) wherein: —R is a (C1-C6)alkyl group; —R? is preferably H; —Ar is a (C5-C12)arylene radical; —X1 is —C(?O)—or —SO2—; and —R? is chosen from the group consisting of possibly substituted (C1-C6)alkyl, heteroaryl, (C5-C12)aryl, and (hetero)cycloalkyl groups, or a pharmaceutically acceptable salt and/or tautomeric form thereof, or its racemates, diastereomers or enantiomers.Type: GrantFiled: November 6, 2018Date of Patent: November 23, 2021Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITÉ D'AIX-MARSEILLE, INSTITUT NATIONAL DE LA SANTE ET DE LA RECHERCHE MEDICALE (INSERM)Inventors: Stéphane Betzi, Sébastien Combes, Yves Collette, Laurent Hoffer, Xavier Morelli, Brigit Raux, Philippe Roche, Iuliia Voitovich
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Patent number: 10948611Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.Type: GrantFiled: May 16, 2018Date of Patent: March 16, 2021Assignees: STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche ScientifiqueInventors: Martin Cochet, Dimitri Soussan, Fady Abouzeid, Gilles Gasiot, Philippe Roche
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Publication number: 20200377522Abstract: The present invention relates to a compound having the following formula (I): (I) wherein: —R is a (C1-C6)alkyl group; —R? is preferably H; —Ar is a (C5-C12)arylene radical; —X1 is —C(?O)— or —SO2—; and —R? is chosen from the group consisting of possibly substituted (C1-C6)alkyl, heteroaryl, (C5-C12)aryl, and (hetero)cycloalkyl groups, or a pharmaceutically acceptable salt and/or tautomeric form thereof, or its racemates, diastereomers or enantiomersType: ApplicationFiled: November 6, 2018Publication date: December 3, 2020Inventors: Stéphane BETZI, Sébastien COMBES, Yves COLLETTE, Laurent HOFFER, Xavier MORELLI, Brigit RAUX, Philippe ROCHE, Iuliia VOITOVICH
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Patent number: 10771048Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.Type: GrantFiled: January 20, 2020Date of Patent: September 8, 2020Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Capucine Lecat-Mathieu De Boissac, Fady Abouzeid, Gilles Gasiot, Philippe Roche, Victor Malherbe
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Publication number: 20200252059Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.Type: ApplicationFiled: January 20, 2020Publication date: August 6, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Capucine LECAT-MATHIEU DE BOISSAC, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE, Victor MALHERBE
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Publication number: 20190292186Abstract: This invention relates to xanthine derivative compounds that are inhibitors of BET bromodomains proteins, the method of preparation thereof and applications thereof.Type: ApplicationFiled: December 27, 2016Publication date: September 26, 2019Inventors: Xavier MORELLI, Sébastien COMBES, Jean-Claude GUILLEMOT, Stéphanie BETZI, Yves COLLETTE, Philippe ROCHE, Adrein LUGARI, Sabine MILHAS, Brigit RAUX, luliia VOITOVICH
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Patent number: 10386414Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.Type: GrantFiled: May 28, 2015Date of Patent: August 20, 2019Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SASInventors: Jean-Marc Daveau, Philippe Roche, Didier Fuin
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Publication number: 20180335526Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.Type: ApplicationFiled: May 16, 2018Publication date: November 22, 2018Applicants: STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche ScientifiqueInventors: Martin COCHET, Dimitri SOUSSAN, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE
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Publication number: 20170205461Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.Type: ApplicationFiled: May 28, 2015Publication date: July 20, 2017Inventors: Jean-Marc DAVEAU, Philippe ROCHE, Didier FUIN
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Patent number: 9479168Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: GrantFiled: March 26, 2014Date of Patent: October 25, 2016Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Patent number: 9417282Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.Type: GrantFiled: March 19, 2015Date of Patent: August 16, 2016Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Jean-Marc Daveau, Sylvain Clerc, Philippe Roche
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Publication number: 20150377962Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.Type: ApplicationFiled: March 19, 2015Publication date: December 31, 2015Inventors: Jean-Marc DAVEAU, Sylvain CLERC, Philippe ROCHE
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Publication number: 20140292374Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: ApplicationFiled: March 26, 2014Publication date: October 2, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Patent number: 8570060Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.Type: GrantFiled: May 19, 2011Date of Patent: October 29, 2013Assignee: STMicroelectronics SAInventors: Sylvain Clerc, Fabian Firmin, Philippe Roche
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Patent number: 8565030Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.Type: GrantFiled: September 22, 2011Date of Patent: October 22, 2013Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche ScientifiqueInventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
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Publication number: 20120081978Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.Type: ApplicationFiled: September 22, 2011Publication date: April 5, 2012Applicants: STMicroelectronics S.A., Centre National de la Recherche Scientifique, STMicroelectronics Crolles 2 SASInventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
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Publication number: 20110291696Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.Type: ApplicationFiled: May 19, 2011Publication date: December 1, 2011Applicant: STMicroelectronics SAInventors: Sylvain Clerc, Fabian Firmin, Philippe Roche
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Publication number: 20110246811Abstract: The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.Type: ApplicationFiled: March 29, 2011Publication date: October 6, 2011Applicants: STMicroelectronics SAInventors: Josep Torras Flaquer, Jean-Marc Daveau, Lirida Naviner, Philippe Roche