Abstract: The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Abstract: The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.

Abstract: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract: A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.

Abstract: A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.

Abstract: An integrated electronic circuit comprises active components disposed on the surface of a substrate and connected by electrical connections disposed within a metallization level. A dielectric material situated between the surface of the substrate and the metallization level, or in the metallization level, has a locally higher value of dielectric permittivity so as to selectively increase a capacitance between certain portions of the active components or of the connections. An electrical state of the circuit in operation is then stabilized, thanks to a higher electrical charge carried by the portions of the active components or of the connections whose capacitance is enhanced. The circuit can be a static random access memory cell.

Abstract: The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.

Abstract: A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.

Abstract: A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.