Patents by Inventor Philippe Soussan
Philippe Soussan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378720Abstract: According to an aspect of the present inventive concept there is provided a light emitting unit, for emitting laser light at a laser wavelength, arranged on a planar surface of a substrate. The unit comprises a first reflective element to reflect light at the laser wavelength, a gain element to amplify the light, and a second reflective element to partially reflect the light, and to emit the laser light. The elements form a stack of layers integrated onto the planar surface. Each layer is parallel with the planar surface, and the gain element is arranged between the first and second reflective elements. The unit comprises a beam shaping element integrated with the stack. The beam shaping element is configured to shape the emitted laser light. The beam shaping element comprises a plurality of structures spaced apart in a direction of an extension of a layer of the beam shaping element. A size of the structures and/or a distance between adjacent structures is smaller than the laser wavelength.Type: ApplicationFiled: May 16, 2023Publication date: November 23, 2023Inventors: Philippe SOUSSAN, Charles CAER, Xavier ROTTENBERG
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Publication number: 20230154914Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed.Type: ApplicationFiled: November 15, 2022Publication date: May 18, 2023Inventors: Gauri Karve, Yunlong Li, Luc Haspeslagh, Philippe Soussan, Deniz Sabuncuoglu Tezcan
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Patent number: 11282702Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.Type: GrantFiled: October 12, 2020Date of Patent: March 22, 2022Assignee: IMEC VZWInventors: Philippe Soussan, Vasyl Motsnyi, Luc Haspeslagh, Stefano Guerrieri, Olga Syshchyk, Bernardette Kunert, Robert Langer
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Publication number: 20210384700Abstract: The disclosure relates to a method for processing a laser device, for example a III-V on silicon laser, including: providing a carrier substrate; forming a grating structure on the carrier substrate, wherein the grating structure delimits a cavity on a surface of the carrier substrate; placing a die in the cavity and bonding the die to the carrier substrate, wherein the die comprises an active region including a III-V semiconductor material; transferring the die from the carrier substrate to a silicon substrate by bonding an exposed side of the die to the silicon substrate and subsequently debonding the carrier substrate from the die; and forming a photonic structure, for example a silicon waveguide, coupled to the die.Type: ApplicationFiled: June 7, 2021Publication date: December 9, 2021Inventors: Charles Caer, Philippe Soussan, Deniz Sabuncuoglu Tezcan, Gauri Karve, Yunlong Li
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Publication number: 20210111021Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.Type: ApplicationFiled: October 12, 2020Publication date: April 15, 2021Inventors: Philippe SOUSSAN, Vasyl MOTSNYI, Luc HASPESLAGH, Stefano GUERRIERI, Olga SYSHCHYK, Bernardette KUNERT, Robert LANGER
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Patent number: 10481348Abstract: There is provided an optical system for coupling light into a waveguide. The optical system comprising a coupler arranged at a portion of the waveguide. The coupler has a surface with a grating structure for directing light into the waveguide formed therein. A cladding layer embeds the coupler and an optical path changing structure is formed in the cladding layer. The optical path changing structure has a refractive surface and a reflective surface, each forming an acute angle with respect to the surface of the coupler. Light which enters the optical path changing structure through the refractive surface will be refracted and directed towards the reflective surface. The reflective surface is arranged to reflect the light such that it is directed towards the grating structure of the coupler along a direction suitable for efficient coupling of light into the waveguide.Type: GrantFiled: August 29, 2017Date of Patent: November 19, 2019Assignee: miDiagnostics NVInventors: Jeonghwan Song, Pol Van Dorpe, Giuseppe Fiorentino, Philippe Soussan, Xavier Rottenberg
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Patent number: 10271796Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.Type: GrantFiled: April 24, 2015Date of Patent: April 30, 2019Assignee: IMECInventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
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Patent number: 10128123Abstract: Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.Type: GrantFiled: May 19, 2016Date of Patent: November 13, 2018Assignee: IMEC VZWInventors: Bivragh Majeed, Philippe Soussan
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Patent number: 9929206Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.Type: GrantFiled: June 23, 2016Date of Patent: March 27, 2018Assignee: IMEC vzwInventors: Bart Vereecke, Deniz Sabuncuoglu Tezcan, Philippe Soussan, Nicolaas Tack
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Publication number: 20180074271Abstract: There is provided an optical system for coupling light into a waveguide. The optical system comprising a coupler arranged at a portion of the waveguide. The coupler has a surface with a grating structure for directing light into the waveguide formed therein. A cladding layer embeds the coupler and an optical path changing structure is formed in the cladding layer. The optical path changing structure has a refractive surface and a reflective surface, each forming an acute angle with respect to the surface of the coupler. Light which enters the optical path changing structure through the refractive surface will be refracted and directed towards the reflective surface. The reflective surface is arranged to reflect the light such that it is directed towards the grating structure of the coupler along a direction suitable for efficient coupling of light into the waveguide.Type: ApplicationFiled: August 29, 2017Publication date: March 15, 2018Inventors: Jeonghwan SONG, Pol Van DORPE, Giuseppe FIORENTINO, Philippe SOUSSAN, Xavier ROTTENBERG
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Publication number: 20170005132Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.Type: ApplicationFiled: June 23, 2016Publication date: January 5, 2017Inventors: Bart Vereecke, Deniz Sabuncuoglu Tezcan, Philippe Soussan
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Publication number: 20160343655Abstract: Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are providedType: ApplicationFiled: May 19, 2016Publication date: November 24, 2016Inventors: Bivragh Majeed, Philippe Soussan
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Publication number: 20150297136Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.Type: ApplicationFiled: April 24, 2015Publication date: October 22, 2015Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
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Patent number: 9105621Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.Type: GrantFiled: December 11, 2013Date of Patent: August 11, 2015Assignee: IMECInventors: Philippe Soussan, Melina Lofrano
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Patent number: 9061897Abstract: Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure.Type: GrantFiled: November 9, 2011Date of Patent: June 23, 2015Assignee: IMECInventors: Alain Phommahaxay, Lieve Bogaerts, Philippe Soussan
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Patent number: 9048198Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.Type: GrantFiled: December 21, 2011Date of Patent: June 2, 2015Assignee: IMECInventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
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Patent number: 9000588Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.Type: GrantFiled: August 26, 2013Date of Patent: April 7, 2015Assignee: IMECInventors: Philippe Soussan, Wenqi Zhang, Silvia Armini
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Patent number: 8822330Abstract: A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution.Type: GrantFiled: October 18, 2010Date of Patent: September 2, 2014Assignee: IMECInventors: Philippe Soussan, Eric Beyne, Philippe Muller
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Publication number: 20140175676Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.Type: ApplicationFiled: December 11, 2013Publication date: June 26, 2014Applicant: IMECInventors: Philippe Soussan, Melina Lofrano
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Publication number: 20140054771Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.Type: ApplicationFiled: August 26, 2013Publication date: February 27, 2014Applicant: IMECInventors: Philippe Soussan, Wenqi Zhang, Silvia Armini