Patents by Inventor Philippe Soussan

Philippe Soussan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111021
    Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 15, 2021
    Inventors: Philippe SOUSSAN, Vasyl MOTSNYI, Luc HASPESLAGH, Stefano GUERRIERI, Olga SYSHCHYK, Bernardette KUNERT, Robert LANGER
  • Patent number: 10481348
    Abstract: There is provided an optical system for coupling light into a waveguide. The optical system comprising a coupler arranged at a portion of the waveguide. The coupler has a surface with a grating structure for directing light into the waveguide formed therein. A cladding layer embeds the coupler and an optical path changing structure is formed in the cladding layer. The optical path changing structure has a refractive surface and a reflective surface, each forming an acute angle with respect to the surface of the coupler. Light which enters the optical path changing structure through the refractive surface will be refracted and directed towards the reflective surface. The reflective surface is arranged to reflect the light such that it is directed towards the grating structure of the coupler along a direction suitable for efficient coupling of light into the waveguide.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 19, 2019
    Assignee: miDiagnostics NV
    Inventors: Jeonghwan Song, Pol Van Dorpe, Giuseppe Fiorentino, Philippe Soussan, Xavier Rottenberg
  • Patent number: 10271796
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 30, 2019
    Assignee: IMEC
    Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
  • Patent number: 10128123
    Abstract: Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 13, 2018
    Assignee: IMEC VZW
    Inventors: Bivragh Majeed, Philippe Soussan
  • Patent number: 9929206
    Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: March 27, 2018
    Assignee: IMEC vzw
    Inventors: Bart Vereecke, Deniz Sabuncuoglu Tezcan, Philippe Soussan, Nicolaas Tack
  • Publication number: 20180074271
    Abstract: There is provided an optical system for coupling light into a waveguide. The optical system comprising a coupler arranged at a portion of the waveguide. The coupler has a surface with a grating structure for directing light into the waveguide formed therein. A cladding layer embeds the coupler and an optical path changing structure is formed in the cladding layer. The optical path changing structure has a refractive surface and a reflective surface, each forming an acute angle with respect to the surface of the coupler. Light which enters the optical path changing structure through the refractive surface will be refracted and directed towards the reflective surface. The reflective surface is arranged to reflect the light such that it is directed towards the grating structure of the coupler along a direction suitable for efficient coupling of light into the waveguide.
    Type: Application
    Filed: August 29, 2017
    Publication date: March 15, 2018
    Inventors: Jeonghwan SONG, Pol Van DORPE, Giuseppe FIORENTINO, Philippe SOUSSAN, Xavier ROTTENBERG
  • Publication number: 20170005132
    Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.
    Type: Application
    Filed: June 23, 2016
    Publication date: January 5, 2017
    Inventors: Bart Vereecke, Deniz Sabuncuoglu Tezcan, Philippe Soussan
  • Publication number: 20160343655
    Abstract: Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Inventors: Bivragh Majeed, Philippe Soussan
  • Publication number: 20150297136
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 22, 2015
    Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
  • Patent number: 9105621
    Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: August 11, 2015
    Assignee: IMEC
    Inventors: Philippe Soussan, Melina Lofrano
  • Patent number: 9061897
    Abstract: Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: June 23, 2015
    Assignee: IMEC
    Inventors: Alain Phommahaxay, Lieve Bogaerts, Philippe Soussan
  • Patent number: 9048198
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 2, 2015
    Assignee: IMEC
    Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
  • Patent number: 9000588
    Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 7, 2015
    Assignee: IMEC
    Inventors: Philippe Soussan, Wenqi Zhang, Silvia Armini
  • Patent number: 8822330
    Abstract: A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: September 2, 2014
    Assignee: IMEC
    Inventors: Philippe Soussan, Eric Beyne, Philippe Muller
  • Publication number: 20140175676
    Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 26, 2014
    Applicant: IMEC
    Inventors: Philippe Soussan, Melina Lofrano
  • Publication number: 20140054771
    Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 27, 2014
    Applicant: IMEC
    Inventors: Philippe Soussan, Wenqi Zhang, Silvia Armini
  • Patent number: 8440504
    Abstract: The present invention is related to a method for aligning and bonding a first element (1) and a second element (2), comprising: obtaining a first element (1) having at least one protrusion, the protrusion having a base portion (12) made of a first material and an upper portion (13) made of a second, deformable material, different from the first material; obtaining a second element (2) having a first main surface and second main surface (8) and at least one through-hole between the first and second main surface; placing the first and second element onto each other; receiving in the through-hole of the second element (2) the protrusion of the first element (1), the protrusion being arranged and constructed so as to extend from an opening of the through-hole in the first main surface to a position beyond an opening of the through-hole in the second main surface (8); deforming the deformable portion (13) of the protrusion, such that the deformed portion mechanically fixes the second element (2) on the first el
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: May 14, 2013
    Assignee: IMEC
    Inventors: Philippe Soussan, Wouter Ruythooren, Eric Beyne, Koen De Munck
  • Publication number: 20120279837
    Abstract: An electrostatically actuatable micro electromechanical device is provided with enhanced reliability and lifetime. The electrostatically actuatable micro electromechanical device comprises: a substrate, a first conductor fixed to the top layer of the substrate, forming a fixed electrode, a second conductor fixed to the top layer of the substrate, and a substrate area. The second conductor is electrically isolated from the first conductor and comprises a moveable portion, suspended at a predetermined distance above the first conductor, the moveable portion forming a moveable electrode which approaches the fixed electrode upon applying an actuation voltage between the first and second conductors. The selected substrate surface area is defined as the orthogonal projection of the moveable portion on the substrate between the first and second conductors. In the substrate surface area at least one recess is provided in at least the top layer of the substrate.
    Type: Application
    Filed: March 31, 2009
    Publication date: November 8, 2012
    Applicants: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Ingrid De Wolf, Xavier Rottenberg, Piotr Czarnecki, Philippe Soussan
  • Patent number: 8294976
    Abstract: An electrostatically actuatable micro electromechanical device is provided with enhanced reliability and lifetime. The electrostatically actuatable micro electromechanical device comprises: a substrate, a first conductor fixed to the top layer of the substrate, forming a fixed electrode, a second conductor fixed to the top layer of the substrate, and a substrate area. The second conductor is electrically isolated from the first conductor and comprises a moveable portion, suspended at a predetermined distance above the first conductor, the moveable portion forming a moveable electrode which approaches the fixed electrode upon applying an actuation voltage between the first and second conductors. The selected substrate surface area is defined as the orthogonal projection of the moveable portion on the substrate between the first and second conductors. In the substrate surface area at least one recess is provided in at least the top layer of the substrate.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: October 23, 2012
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Ingrid De Wolf, Xavier Rottenberg, Piotr Czarnecki, Philippe Soussan
  • Publication number: 20120209100
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Application
    Filed: December 21, 2011
    Publication date: August 16, 2012
    Applicant: IMEC
    Inventors: Maria OP DE BEECK, Eric Beyne, Philippe Soussan