Patents by Inventor Phillip Celaya

Phillip Celaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing a semiconductor component
    Patent number: 8324026
    Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, James P. Letterman, Jr., Robert L. Marquis
  • Multi-chip semiconductor connector
    Patent number: 8253239
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 28, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
    Publication number: 20110298115
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 8, 2011
    Inventors: Phillip Celaya, Yeu Wen Lee, Weng Onn Low, Virgilio Abalos, JR., Jamieson Wardall
  • Method for manufacturing a semiconductor component and structure therefor
    Patent number: 8071427
    Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: December 6, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, James P. Letterman, Jr., Robert L. Marquis
  • METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR
    Publication number: 20110281397
    Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Inventors: Phillip Celaya, James P. Letterman, JR., Robert L. Marquis
  • MULTI-CHIP SEMICONDUCTOR CONNECTOR
    Publication number: 20110068451
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Multi-chip semiconductor connector and method
    Patent number: 7875964
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Semiconductor package and method therefor
    Patent number: 7825505
    Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: November 2, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, James P. Letterman, Jr.
  • METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR
    Publication number: 20100187663
    Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Inventors: Phillip Celaya, James P. Letterman, JR., Robert L. Marquis
  • SEMICONDUCTOR PACKAGE AND METHOD THEREFOR
    Publication number: 20100052145
    Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
    Type: Application
    Filed: November 11, 2009
    Publication date: March 4, 2010
    Inventors: Phillip Celaya, James P. Letterman, JR.
  • Semiconductor package and method therefor
    Patent number: 7638863
    Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Phillip Celaya, James P. Letterman, Jr.
  • Multi-chip semiconductor connector assemblies
    Patent number: 7508060
    Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: March 24, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Multi-chip semiconductor connector assembly method
    Patent number: 7498195
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: March 3, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Semiconductor package structure having multiple heat dissipation paths and method of manufacture
    Patent number: 7495323
    Abstract: In one embodiment, a semiconductor package structure includes a conductive bridge having coupling portions on opposing ends. A lead frame includes alignment or receiving features for receiving the coupling portions of the bridge. A semiconductor device is attached to both the conductive bridge and the lead frame, and is configured so that the coupling portions are on opposing sides of the semiconductor device.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: February 24, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Stephen St. Germain, Phillip Celaya, Roger Arbuthnot, Francis J. Carney
  • SEMICONDUCTOR PACKAGE STRUCTURE HAVING MULTIPLE HEAT DISSIPATION PATHS AND METHOD OF MANUFACTURE
    Publication number: 20080054438
    Abstract: In one embodiment, a semiconductor package structure includes a conductive bridge having coupling portions on opposing ends. A lead frame includes alignment or receiving features for receiving the coupling portions of the bridge. A semiconductor device is attached to both the conductive bridge and the lead frame, and is configured so that the coupling portions are on opposing sides of the semiconductor device.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Inventors: Stephen St. Germain, Phillip Celaya, Roger Arbuthnot, Francis J. Carney
  • SEMICONDUCTOR PACKAGE AND METHOD THEREFOR
    Publication number: 20080054424
    Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Phillip Celaya, James P. Letterman
  • MULTI-CHIP SEMICONDUCTOR CONNECTOR ASSEMBLIES
    Publication number: 20080006920
    Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen St. Germain, Jay Yoder
  • Multi-chip semiconductor connector assemblies
    Patent number: 7298034
    Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: November 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • MULTI-CHIP SEMICONDUCTOR CONNECTOR ASSEMBLY METHOD
    Publication number: 20070126107
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 7, 2007
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen Germain, Jay Yoder
  • MULTI-CHIP SEMICONDUCTOR CONNECTOR AND METHOD
    Publication number: 20070126106
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Application
    Filed: February 7, 2007
    Publication date: June 7, 2007
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen St. Germain, Jay Yoder