Patents by Inventor Phillip J. Nigh

Phillip J. Nigh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8176362
    Abstract: A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Monty M Denneau, Vikram Iyengar, Phillip J. Nigh
  • Publication number: 20090241124
    Abstract: A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 24, 2009
    Inventors: Monty M. Denneau, Vikram Iyengar, Phillip J. Nigh
  • Patent number: 7574644
    Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
    Type: Grant
    Filed: June 25, 2005
    Date of Patent: August 11, 2009
    Assignee: International Business Machines Corporation
    Inventors: Donato Forlenza, Franco Molika, Phillip J. Nigh
  • Patent number: 7194706
    Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Leendert M. Huisman, Mark D. Jaffe, Phillip J. Nigh, Leah M. P. Pastel, Thomas G. Sopchak, David E. Sweenor, David P. Vallett
  • Patent number: 7127690
    Abstract: A method and system for defect evaluation using IDDQ voltage linearity provides improved IDDQ testing for determining whether manufacturing defects in a VLSI device are likely to cause functional faults. IDDQ data is collected at multiple power plane voltages (VDDs) for a test vector at which a fault is activated. The IDDQ vs. VDD is then examined and a range of VDDs over which the characteristic IDDQs are non-linear with respect to VDD is determined. Peaks in the first derivative of the IDDQ vs. VDD curve indicate a particular VDD at which the onset of non-linearity in the IDDQ occurs. The VDD point below which the curve is non-linear indicates the relative resistance of a fault with respect to the driving point resistance of the node at which the fault is located. The relative resistance is directly determinative of additional circuit delay cause by the fault and/or whether the fault will cause a logic level transmission failure.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: October 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anne Elizabeth Gattiker, Phillip J. Nigh
  • Patent number: 7089514
    Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Greg Bazan, John M. Cohn, Francis Gravel, Leendert M. Huisman, Phillip J. Nigh, Leah M. P. Pastel, Kenneth Rowe, Thomas G. Sopchak, David E. Sweenor
  • Patent number: 7017095
    Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Donato Forlenza, Franco Motika, Phillip J. Nigh
  • Patent number: 6998866
    Abstract: A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Greg Bazan, John M. Cohn, Matthew S. Grady, Phillip J. Nigh, Leah M. P. Pastel, Thomas G. Sopchak
  • Patent number: 6961886
    Abstract: A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: November 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: Franco Motika, Phillip J. Nigh, Phong T. Tran
  • Publication number: 20040210808
    Abstract: A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Applicant: International Business Machines Corporation
    Inventors: Franco Motika, Phillip J. Nigh, Phong T. Tran
  • Patent number: 6763314
    Abstract: A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Phillip J. Nigh, Jody J. Van Horn
  • Patent number: 6751765
    Abstract: An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 15, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard F. Rizzolo, Rocco E. DeStefano, Joseph E. Eckelman, Thomas G. Foote, Steven Michnowski, Franco Motika, Phillip J. Nigh, Bryan J. Robbins
  • Publication number: 20040010741
    Abstract: A method of diagnosing complex semiconductor device functional testing failures by combining deterministic and functional testing with diagnostic techniques. The method determines the failing logic locations by creating a new test pattern based on the functional failure by transforming a functional pattern into a scan deterministic pattern so that existing diagnostic tools can also be used to determine the location of and type of error in the failing circuit without impacting manufacturing test. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Applicant: International Business Machines Corporation
    Inventors: Donato Forlenza, Franco Motika, Phillip J. Nigh
  • Patent number: 6650130
    Abstract: A method of and apparatus (10) for detecting one or more defects (130) in a plurality of chips (110) on a wafer (40). The method comprises a first step of simultaneously providing electrical power to the plurality of chips, thereby generating one or more light signals (120) corresponding to the one or more defects in the plurality of chips. The second step is simultaneously forming an image (150) of the plurality of chips so as to simultaneously detect the one or more light signals. The apparatus (10) for carrying out the method comprises electrical probes (30) for providing electrical power to the plurality of chips, a detector (60) to detect the one or more light signals emitted by the chips as a result of electrical power interacting with the one or more defects, and an imaging system (50) arranged so as to form an image of the plurality of chips, including the light signals, onto the detection surface (64).
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey A. Kash, Phillip J. Nigh, David P. Vallet
  • Patent number: 6650768
    Abstract: A system and method for determining the location of a particular device on an integrated circuit chip is described. The system and method utilize apparatus for detecting the emission of light during switching events of devices in the circuit during the circuit's processing of an input calculated to actuate the device whose location is desired. Light emissions from the circuit can be temporally and spatially indexed so as to allow deduction, in combination with the a priori knowledge of the logical operation of the circuit, of the location of the desired element. In another embodiment of the invention, a series of images of the circuit can be accumulated, representing the circuit's response to a series of different input signals, each input signal being designed to result in the switching of the desired element. The series of images can be compared to determine the location of the desired element.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard James Evans, Jeffrey Alan Kash, Daniel Ray Knebel, Phillip J Nigh, Pia Naoko Sanda, James Chen-Hsiang Tsang, David Paul Vallett
  • Patent number: 6618682
    Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Raymond J. Bulaga, Anne E. Gattiker, John L. Harris, Phillip J. Nigh, Leo A. Noel, William J. Thibault, Jody J. Van Horn, Donald L. Wheater
  • Publication number: 20030131294
    Abstract: While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying an operating parameters such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated varying each of the selected operating parameters with the latch position following the stuck-at fault latch is identified.
    Type: Application
    Filed: January 10, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Franco Motika, Phillip J. Nigh, Peilin Song
  • Publication number: 20030065484
    Abstract: A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Phillip J. Nigh, Jody J. Van Horn
  • Patent number: 6516432
    Abstract: Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: February 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Franco Motika, Phillip J. Nigh, Peilin Song, Howard B. Druckerman
  • Publication number: 20020155628
    Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 24, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond J. Bulaga, Anne E. Gattiker, John L. Harris, Phillip J. Nigh, Leo A. Noel, William J. Thibault, Jody J. Van Horn, Donald L. Wheater