Patents by Inventor Phillip J. Nigh

Phillip J. Nigh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6442723
    Abstract: LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Koprowski, Franco Motika, Phillip J. Nigh
  • Patent number: 6304668
    Abstract: A system and method for determining the location of a particular device on an integrated circuit chip is described. The system and method utilize apparatus for detecting the emission of light during switching events of devices in the circuit during the circuit's processing of an input calculated to actuate the device whose location is desired. Light emissions from the circuit can be temporally and spatially indexed so as to allow deduction, in combination with the a priori knowledge of the logical operation of the circuit, of the location of the desired element. In another embodiment of the invention, a series of images of the circuit can be accumulated, representing the circuit's response to a series of different input signals, each input signal being designed to result in the switching of the desired element. The series of images can be compared to determine the location of the desired element.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: October 16, 2001
    Assignee: International Business Machines Corporation
    Inventors: Richard James Evans, Jeffrey Alan Kash, Daniel Ray Knebel, Phillip J Nigh, Pia Naoko Sanda, James Chen-Hsiang Tsang, David Paul Vallett
  • Patent number: 6125461
    Abstract: A system and method for identifying long paths in an integrated circuit are described. An integrated circuit chip is subjected to input test signals of progressively shorter cycle time until the chip fails to produce a correct output. The cycle time of the signal resulting in the failure of the chip is defined as T. A signal having cycle time T'=T+.DELTA.T is then applied to the integrated circuit, where the signal of cycle time T' is known to result in proper operation of the chip. The chip is then observed for switching activity during the period .DELTA.T which occurs beginning at a time T measured from the beginning of the second signal of duration T' until the end of the signal of duration T'. The location of the switching activity is used to identify the path or paths of the circuit that resulted in failure of the chip. In a preferred embodiment of the invention, the switching activity is detected using an optical measurement system capable of detecting light generated by transistor switching activity.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: September 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Leendert Marinus Huisman, Daniel Ray Knebel, Phillip J Nigh, Pia Naoko Sanda, Xiaodong Xiao
  • Patent number: 5930270
    Abstract: A system and method for diagnosing the faults of an electronic device by running a series of tests, identifying the tests where the electronic device failed, without having to check the results of each test, storing information generated during only the tests where the electronic device failed, and using the information to diagnose the faults in the electronic device. The test results are accumulated into a Multiple Input Shift Register (MISR) which need not be examined after each test to determine which tests the device failed. The problem of a failure during one test manifesting into the MISR during subsequent tests is handled by predicting the effect of the failure on the MISR during subsequent tests.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Donato O. Forlenza, Franco Motika, John J. Shushereba, Phillip J. Nigh
  • Patent number: 5025344
    Abstract: A built in current sensor on a unitary substrate with an integrated circuit is provided to sense abnormal quiescent current flow through the integrated circuit after a timing phase as an indication of defects such as shorts and open circuits, while ignoring normal high current peaks. A comparator is provided along with an adjustable reference current to provide a virtual ground voltage which represents that induced by a normal quiescent current through a fault-free integrated circuit. A breaker circuit may be provided for indication, or power disconnection of the integrated circuit, upon the occurrence of current flow above a predetermined value.
    Type: Grant
    Filed: February 22, 1990
    Date of Patent: June 18, 1991
    Assignee: Carnegie Mellon University
    Inventors: Wojciech P. Maly, Phillip J. Nigh