Abstract: An artificial hand, a kit of components for making the artificial hand and a method of making and installing the artificial hand on the arm stump of a person in need thereof. This artificial hand is made of relatively low-cost components and is fairly easy to assemble from a kit of such components. Additionally, the artificial hand can be relatively quickly and easily fit to the arm stump of a person in need thereof so that the person can wear and use the artificial hand immediately without excessive training or instructions.

Abstract: An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

Abstract: In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

Abstract: In one embodiment, a phase locked loop (PLL) circuit in a device includes selectable feedback paths and a multiplexer. An internal feedback path is adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of the device and an external feedback path is adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device. The multiplexer is provided for selecting between the internal and external feedback paths.

Abstract: In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

Abstract: In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

Abstract: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

Abstract: Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

Abstract: In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract: In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.

Abstract: A cotter pin includes first and second tines having flat confronting surfaces and curved side surfaces with flat outer surfaces substantially parallel to the flat confronting surfaces thereof.

Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.

Abstract: Mask (10, 10?, 21, 22, 30) for use in coating a carbon-carbon composite brake disc (25) with anti-oxidant. The mask is composed of carbon-carbon composite material or nonreactive ceramic material. The mask is configured with edge ridges (11, 13, 34, 36) that are aligned with the outer and inner annular diameters of the carbon-carbon composite brake disc, a gas flow channel (12, 32) between the ridges, and a gas access port (18, 40) that allows gas to enter the gas flow channel. The mask may also include a gas exit port (16) having a valve (17) operatively connected thereto, so that gas flow may be restricted when pressure within the mask and carbon-carbon composite brake disc falls below a specified minimum value.

Abstract: Embodiments of the present invention provide an anchor assembly configured to be secured to a panel. The anchor assembly includes a main body, a double-sided adhesive, and a fastening member. The main body includes a base, wherein a through-hole is formed through the base. The double-sided adhesive is attached to one side of the base. The fastening member is retained within the through-hole. The fastening member may be manufactured with the main body and the double-sided adhesive as a single piece.

Abstract: Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

Abstract: In one embodiment of the invention, a phase-locked loop (PLL) can be programmably controlled to add jitter to its PLL output clock. Such a PLL can be used to programmably inject jitter into the outgoing serial data signal generated by a serializer/de-serializer (serdes) that can be operated in an internal loopback mode, in which the outgoing serial data signal is internally looped back from the transmitter side of the serdes to the serdes receiver side. Jitter logic associated with the PLL can be operated in a register-based mode that does not rely on any externally generated jitter clock. Such register-based processing enables effective (1) internal loopback testing of unpackaged devices at the wafer stage as well as package devices at the package stage and (2) external loopback testing at the system level.

Abstract: A cotter pin includes first and second tines having flat confronting surfaces and curved side surfaces with flat outer surfaces substantially parallel to the flat confronting surfaces thereof.