Abstract: The present invention provides a look ahead architecture to satisfy the retransmit recovery time constraints in a mark and retransmit system while allowing a full bitline precharge. A number of sense amplifiers are provided in the look ahead architecture that may be equipped with a "shadow latch" to store the read data when the mark pointer is asserted. As a result, the data to be retransmitted will be retrieved from the shadow latches when the retransmit is asserted, allowing a full precharge cycle before reading from the memory array.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: The present invention provides an efficient design that can be used to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A state machine design which can be used to realize extremely short flag generation delays, also realizing the benefit of having an extremely high MTBF. A set of next state variables are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

Abstract: A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag.

Abstract: The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic to eliminate glitches in the inputs to a full/empty flag generator, an almost full/almost empty flag generator or a half-full/half-empty flag generator. The circuit can be extended to generate the logic to eliminate glitches in either direction as the count signals move across a boundary change in a half-full flag generation circuit.

Abstract: The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.