Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.

Abstract: Octagonal phase rotator apparatus is provided for producing an output signal that is phase dependent on a digital control code. The apparatus includes an I-mixer, a Q-mixer, and first and second IQ-mixers. The I-mixer is responsive to I-control bits of the digital control code. The Q-mixer is responsive to Q-control bits of the digital control code. The first and second IQ-mixers are respectively responsive to one or more IQ1-control bits and one or more IQ2-control bits of the digital control code. The I-mixer comprises an I-DAC for steering current between a positive phase IP and a negative phase IN of an in-phase (I) signal wherein the one or more I-control bits control switching of a first current unit between IP and IN, and a set of amplifiers for weighting the phases IP and IN, in dependence on current steered to each phase by the I-DAC, to produce a weighted I-signal.

Abstract: A decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs, including at least one decision-feedback equalizer block comprising a plurality of speculation units. Each speculation unit includes a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a given threshold voltage; and an arrangement for selectively generating a transconductor current which depends on the amplified voltage difference. Also included is one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.

Abstract: A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.

Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Abstract: A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.

Abstract: A decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs, including at least one decision-feedback equalizer block comprising a plurality of speculation units. Each speculation unit includes a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a given threshold voltage; and an arrangement for selectively generating a transconductor current which depends on the amplified voltage difference. Also included is one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.

Abstract: A continuous time linear equalizer and method of operation. The equalizer includes circuitry configured to provide a high-pass transfer function having a peaking frequency to equalize an input signal into an output signal. The circuitry includes an input gain stage configured to receive an input signal and to provide a gain; and an active peaking stage configured to set the gain at a peaking frequency. A bandwidth extension unit is configured to shift the peaking frequency of the continuous time linear equalizer to a higher frequency.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream. The early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value. The selecting is performed depending on the early/late signal and depending on the phase rotation counter value.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value.

Abstract: Embodiments are directed to feed-forward equalization. In some embodiments, a first circuit is configured to receive a signal transmitted over a channel as a differential pair, and a second circuit is configured to mirror the signal as at least a pre-cursor component comprising a first transistor of a first type of technology, a cursor component comprising a second transistor of a second type of technology, and a post-cursor component comprising a third transistor of the first type of technology.

Abstract: Embodiments are directed to feed-forward equalization. In some embodiments, a first circuit is configured to receive a signal transmitted over a channel as a differential pair, and a second circuit is configured to mirror the signal as at least a pre-cursor component comprising a first transistor of a first type of technology, a cursor component comprising a second transistor of a second type of technology, and a post-cursor component comprising a third transistor of the first type of technology.

Abstract: A circuit design configured to process a differential input signal is provided. A first floating capacitor ladder is configured to receive the positive of the differential input signal and is connected to a first switched capacitor network through phase one controlled switches. A second floating capacitor ladder configured to receive the negative of the differential input signal and is connected to a second switched capacitor network through other phase one controlled switches. A reference resistor ladder is connected to the first switched capacitor network through phase two controlled switches to provide voltage references and connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references.

Abstract: A circuit design configured to process a differential input signal is provided. A first floating capacitor ladder is configured to receive the positive of the differential input signal and is connected to a first switched capacitor network through phase one controlled switches. A second floating capacitor ladder configured to receive the negative of the differential input signal and is connected to a second switched capacitor network through other phase one controlled switches. A reference resistor ladder is connected to the first switched capacitor network through phase two controlled switches to provide voltage references and connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references.