Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: DC-DC voltage regulators for converting an input voltage into one or more output voltages and methods for operating such voltage regulators are described. The voltage regulator may have a high side switching device coupled between the input port and a first intermediate node. The voltage regulator may have an inductive element having one port coupled to the first intermediate node and may have a capacitive element having two ports, coupled between the first intermediate node and a second intermediate node, with its one port coupled to the first intermediate node. The voltage regulator may have a charging switching device coupled between the other port of the capacitive element and a predetermined voltage level, for charging the capacitive element when the high side switching device and the charging switching device are both in an ON state.

Abstract: DC-DC voltage regulators for converting an input voltage into one or more output voltages and methods for operating such voltage regulators are described. The voltage regulator may have a high side switching device coupled between the input port and a first intermediate node. The voltage regulator may have an inductive element having one port coupled to the first intermediate node and may have a capacitive element having two ports, coupled between the first intermediate node and a second intermediate node, with its one port coupled to the first intermediate node. The voltage regulator may have a charging switching device coupled between the other port of the capacitive element and a predetermined voltage level, for charging the capacitive element when the high side switching device and the charging switching device are both in an ON state.

Abstract: Circuits and methods to achieve a hysteretic buck-boost converter system, separating buck and boost pulses based on monitoring a difference between the output voltage of the buck-boost converter and a reference voltage (error voltage) or alternatively based on monitoring additionally coil current or load current or both currents have been disclosed. The performance of the buck-boost converter can be further improved by using an optional output voltage change block monitoring if the output voltage rises or falls. The buck-boost converter disclosed has a very simple topology without a modulator block, which is regulating the duty cycle and without frequency compensation.

Abstract: Circuits and methods to achieve a hysteretic buck-boost converter system, separating buck and boost pulses based on monitoring a difference between the output voltage of the buck-boost converter and a reference voltage (error voltage) or alternatively based on monitoring additionally coil current or load current or both currents have been disclosed. The performance of the buck-boost converter can be further improved by using an optional output voltage change block monitoring if the output voltage rises or falls. The buck-boost converter disclosed has a very simple topology without a modulator block, which is regulating the duty cycle and without frequency compensation.

Abstract: The present document relates to a pre-charge circuit of electronic circuits having Miller compensation and significant output capacitance such as LDOs or multistage amplifiers. The pre-charge circuit limits an inrush current right after enabling of the electronic circuit. The pre-charge circuit limits and clamps the fast charging of the Miller capacitor. A delay circuit disables the pre-charge circuit when the bias conditions of the Miller capacitor are close to normal bias conditions.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: An apparatus of an exponential current digital-to-analog converter (IDAC) using a binary-weighted MSB to efficiently drive current controlled light emitting diode (LED) devices. The apparatus comprises of an exponential current digital-to-analog converter (IDAC) current source, a voltage buffer to create an active cascode at the output stage, and an error amplifier that by means of a DC-DC converter voltage loop imposes an appropriate voltage at the output of the IDAC, depending on the current load set to drive the LEDs. The definition of the apparatus involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: An apparatus of an exponential current digital-to-analog converter (IDAC) using a binary-weighted MSB to efficiently drive current controlled light emitting diode (LED) devices. The apparatus comprises of an exponential current digital-to-analog converter (IDAC) current source, a voltage buffer to create an active cascode at the output stage, and an error amplifier that by means of a DC-DC converter voltage loop imposes an appropriate voltage at the output of the IDAC, depending on the current load set to drive the LEDs. The definition of the apparatus involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology.

Abstract: The present document relates to switching DC converters In particular, the present document relates to creating an auxiliary reference voltage for the switching converter to implement a dynamic correction of static load regulation. Main objective of the disclosure is minimizing the regulation error on account of accuracy when non-idealities present in the regulation loop are considered. An additional control loop to monitor the regulated error signal has been added. The additional loop has the purpose to create an auxiliary reference for the boost converter which will be updated (up and down) whenever the regulation exceeds a target threshold.

Abstract: A current mode control buck-boost converter with improved performance utilizes separate buck and boost pulses. The buck-boost converter utilizes a buck/boost decision method with continuous control voltage for buck and boost mode, therefore eliminating transients in the control loop between operation modes and preventing voltage overshoots. If switching in Boost mode and the buck duty cycle is smaller than a set duty cycle, then in the next cycle Buck mode switching will occur. It is possible to track a Buck comparator output and the related duty cycle during Boost mode operation. Thus a mode change decision will only be dependent on a single input. A control loop will incorporate a single loop filter and error amplifier, wherein control voltages for Buck comparator and Boost comparator will be related.

Abstract: The present document relates to switching DC converters In particular, the present document relates to creating an auxiliary reference voltage for the switching converter to implement a dynamic correction of static load regulation. Main objective of the disclosure is minimizing the regulation error on account of accuracy when non-idealities present in the regulation loop are considered. An additional control loop to monitor the regulated error signal has been added. The additional loop has the purpose to create an auxiliary reference for the boost converter which will be updated (up and down) whenever the regulation exceeds a target threshold.

Abstract: A method for the design synthesis of an exponential current digital-to-analog (IDAC) using a binary-weighted MSB. The design synthesis involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) comprising (1) defining a differential non-linearity (DNL); (2) defining number of LSB bits needed for the targeted DNL with a binary weighted MSB; (3) calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base; (4) deriving the minimum current for the Imax; (5) defining the LSB as an exponential current mirror according to the specified relationship for the ILSB; and (6) defining a binary-weighted MSB according to the specified relationship for IMSB.

Abstract: A current mode control buck-boost converter with improved performance utilizes separate buck and boost pulses. The buck-boost converter utilizes a buck/boost decision method with continuous control voltage for buck and boost mode, therefore eliminating transients in the control loop between operation modes and preventing voltage overshoots. If switching in Boost mode and the buck duty cycle is smaller than a set duty cycle, then in the next cycle Buck mode switching will occur. It is possible to track a Buck comparator output and the related duty cycle during Boost mode operation. Thus a mode change decision will only be dependent on a single input. A control loop will incorporate a single loop filter and error amplifier, wherein control voltages for Buck comparator and Boost comparator will be related.

Abstract: A method for the design synthesis of an exponential current digital-to-analog (IDAC) using a binary-weighted MSB. The design synthesis involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) comprising (1) defining a differential non-linearity (DNL); (2) defining number of LSB bits needed for the targeted DNL with a binary weighted MSB; (3) calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base; (4) deriving the minimum current for the Imax; (5) defining the LSB as an exponential current mirror according to the specified relationship for the ILSB; and (6) defining a binary-weighted MSB according to the specified relationship for IMSB.

Abstract: An apparatus of an exponential current digital-to-analog converter (IDAC) using a binary-weighted MSB to efficiently drive current controlled light emitting diode (LED) devices. The apparatus comprises of an exponential current digital-to-analog converter (IDAC) current source, a voltage buffer to create an active cascode at the output stage, and an error amplifier that by means of a DC-DC converter voltage loop imposes an appropriate voltage at the output of the IDAC, depending on the current load set to drive the LEDs. The definition of the apparatus involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology.