Abstract: The device described permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. It comprises an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to a first supply terminal by means of a conductor which can be broken by means outside the integrated circuit, and to the second supply terminal by means of a capacitor in parallel with a diode connected for reverse conduction. The device described does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, including: a first resistor and a first capacitor which are parallel connected; an operational amplifier; a terminal of a second resistor which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor and the first capacitor; a second capacitor, which is ffeedback-connected between the output of the operational amplifier and the inverting input; and an additional pair of resistors which are arranged so as to provide feedback between the output and the inverting input, a current signal arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

Abstract: The device permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. More specifically, the device provides an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to first and second supply terminals, via a conductor and a capacitor, respectively. The conductor can be broken by means outside the integrated circuit, and the capacitor is connected in parallel with a diode connected for reverse conduction. The device does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.

Abstract: A voltage multiplier includes a first charge transfer capacitor designed to take and transfer electrical charges from the input terminal to the output terminal, a second capacitor for charge storage connected between the output terminal and ground and an output voltage stabilization circuit. The output voltage stabilization circuit includes an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage and the output voltage of the voltage multiplier. The continuous voltage is applied to one terminal of said charge transfer capacitor so that the potential at the other terminal of the capacitor changes proportionally to the output voltage of the voltage multiplier.

Abstract: Electronic switch for low-voltage supply circuits completed with CMOS technology and comprising a first, a second and a third circuit element (SW1 ,SW2,SW3) consisting each of a pair of complementary transistors. The first and second of said elements (SW1,SW2) are inserted between two connection terminals of the switch (A,B) while the third element SW3 is inserted between a node (C) included between the first and the second element of a voltage reference (VCM). The first and second element are driven to conduction in phases (.phi.1) not overlapping the phases (.phi.2) in which it conducts the third element.

Abstract: An initialization circuit for memory registers, having a signal input being applied a supply voltage which rises linearly from a null value, and an initializing output connected to an input of a memory register and on which a voltage signal, being equal or proportional to the supply voltage, during the initialization step, and a null voltage signal, upon the supply voltage dropping below a predetermined tripping value, are produced. Additionally, the circuit has, between the input and the output, a first circuit portion connected to the input; a second circuit portion connected after the first and having a first output connected to the initializing output; and a third, inverting circuit portion having an input connected to a second output of the second portion and an output connected to the first portion to hold off that first portion while the supply voltage drops below the threshold voltage.

Abstract: An electronic switch having a reduced body effect includes first and second switch terminals. A first transistor of a first type has a control terminal, a first substrate coupled to a first voltage level, and first and second drive terminals respectively coupled to the first and second switch terminals. A second transistor of a second type has a control terminal, a second substrate, a first drive terminal coupled to the second substrate and to the first switch terminal, and a second drive terminal. A third transistor of the second type has a control terminal, a third substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the third substrate and to the second switch terminal. A fourth transistor of a first type has a control terminal, a fourth substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the fourth substrate and a first voltage level.

Abstract: A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.

Abstract: A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

Abstract: A driver circuit, for an electronic switch which is to be operated from a clock signal, comprises an inverter driven by the clock signal, and a voltage doubler which is connected to supply the inverter and connected to be driven by the complementary clock signal.

Abstract: An initialization circuit, particularly for memory registers, being of a type which comprises a signal input to which a supply voltage is applied, and an initialization output at which a voltage signal is produced which is equal to the supply voltage up to a predetermined tripping value for the circuit, further comprises a second output connected to the register and being also an initialization output driven to a null voltage value upon the supply voltage dropping below the tripping value.

Abstract: The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.

Abstract: An all-differential operational amplifier (20) has a first input (22) and a second input (24) and correspondingly has a first output (26) and a second output (28), fed back on its own input respectively through a first (34) and second (36) impedance which are generally resistive and have identical values. The first output is connected to the second input of the operational amplifier across a third impedance (32). A fourth impedance (30), equal in value to the third impedance, is connected in series to the first input and acts as input terminal of the converter. The resistive components of the impedance can be implemented as switched capacitors.

Abstract: A high resolution, fully differential, CMOS comparator advantageously employs a single high-gain, "folded cascode", fully differential operational amplifier and an output latch circuit and the output common mode control of the high-gain amplifier is implemented without requiring the use of a conventional control circuit, thus improving layout economy. The common mode control is performed by providing the latch with a differential input stage through which a common mode feedback network is realized which acts upon a pair of output transistors of the operational amplifier for effectively controlling the output common mode thereof. The comparator has a simplified layout and is remarkably faster because it has no additional capacitances loading the outputs of the amplifier.

Abstract: The TTL-compatible cell comprising two cascade coupled CMOS inverters is associated with an input pin of the integrated circuit to make it suitable to receive signals in TTL logic, as well as with a power-down pin, and is characterized in that said input (10) of the CMOS integrated circuit is connected to the input of the first of said two inverters (12, 14) through a first and a second respectively P-channel and N-channel MOS transistor in parallel (28, 30), the first controlled by the power-down pin (31), the second by an inverter (32) driven by said power-down pin, so as to be both off when the power-down signal is at logical 1 and active when the power-down signal is at logical 0. Between the input of the first inverter and the ground a further MOS transistor (34) is connected the gate whereof is controlled so that said further MOS transistor is active when the power-down signal is at logical 1 and is off when the power-down signal is at logical 0.

Abstract: The antibounce circuit comprises:(a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal;(b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate;(c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate;(d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.

Abstract: In a Pulse Code Modulated (PCM) circuit chip, apparatus in the transmit path to compensate for an offset voltage signal from a band-pass filter includes an up-down counter which is actuated to provide a digital value equivalent to the offset signal and a digital to analog converter coupled to the counter to provide an analog signal representing the digital value in the counter. During an initialization phase, the counter is incremented until the digital value of the counter provides, by means of the digital to analog converter, an analog signal that compensates for the off-set signal. After the initialization phase when the band-pass filter's offset voltage is compensated, then other circuitry including an exclusive OR gate and an associated overflow counter are used to eneable or disable the up-down counter to insure that the PCM output signal is an accurate representation of the analog input signal.

Abstract: A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.

Abstract: In a buffer with an operational amplifier having two inputs and two outputs and two feedback capacitances are inserted two other capacitances which in the measurement stage are switched in parallel to the feedback ones with opposite sign in such a manner as to cancel out the effects on the output voltage signal.