Patents by Inventor Pierangelo Magni

Pierangelo Magni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901250
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectron S.r.l.
    Inventors: Pierangelo Magni, Michele Derai
  • Patent number: 11842954
    Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: December 12, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Pierangelo Magni
  • Publication number: 20230143539
    Abstract: A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 11, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Pierangelo MAGNI
  • Patent number: 11552024
    Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Michele Derai, Pierangelo Magni
  • Publication number: 20220406703
    Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.
    Type: Application
    Filed: August 31, 2022
    Publication date: December 22, 2022
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: Pierangelo MAGNI
  • Publication number: 20220392830
    Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 8, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Pierangelo MAGNI
  • Patent number: 11462465
    Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 4, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventor: Pierangelo Magni
  • Patent number: 11417590
    Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Pierangelo Magni
  • Publication number: 20220068741
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Michele DERAI
  • Publication number: 20220059369
    Abstract: A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 24, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco ROVITTO, Pierangelo MAGNI, Fabio MARCHISI
  • Publication number: 20210167000
    Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Pierangelo MAGNI
  • Publication number: 20210050299
    Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 18, 2021
    Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Michele DERAI, Pierangelo MAGNI
  • Patent number: 10879143
    Abstract: A method of manufacturing semiconductor devices includes providing one or more semiconductor chips having a surface with electrical contact pads and a package mass encapsulating the semiconductor chip. The package mass includes a recessed portion leaving the semiconductor chip surface with the contact pads exposed, the recessed portion having a peripheral wall extending from the surface of the semiconductor chip to the outer surface of the package mass. Electrically-conductive formations are provided extending over the peripheral wall of the recessed portion with proximal ends electrically coupled with the contact pads of the semiconductor chip and distal ends at the outer surface of the package mass. The recessed portion is filled with a further package mass by leaving the distal ends of the electrically-conductive formations uncovered.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 29, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Federico Giovanni Ziglioli, Pierangelo Magni
  • Publication number: 20200321274
    Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventor: Pierangelo MAGNI
  • Patent number: 10522504
    Abstract: In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 31, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Pierangelo Magni, Alberto Arrigoni
  • Publication number: 20180342433
    Abstract: A method of manufacturing semiconductor devices includes providing one or more semiconductor chips having a surface with electrical contact pads and a package mass encapsulating the semiconductor chip. The package mass includes a recessed portion leaving the semiconductor chip surface with the contact pads exposed, the recessed portion having a peripheral wall extending from the surface of the semiconductor chip to the outer surface of the package mass. Electrically-conductive formations are provided extending over the peripheral wall of the recessed portion with proximal ends electrically coupled with the contact pads of the semiconductor chip and distal ends at the outer surface of the package mass. The recessed portion is filled with a further package mass by leaving the distal ends of the electrically-conductive formations uncovered.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 29, 2018
    Inventors: Federico Giovanni ZIGLIOLI, Pierangelo MAGNI
  • Patent number: 10141240
    Abstract: A semiconductor device includes a layered package having a semiconductor die embedded therein, the semiconductor die coupled with a thermally-conductive element. The layered package includes, e.g., PCB boards with an intermediate layer having the semiconductor die arranged therein, and a pair of outer layers, with the thermally-conductive element including a thermally-conductive inlay in one of the outer layers.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 27, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Pierangelo Magni
  • Publication number: 20180190563
    Abstract: A semiconductor device includes a layered package having a semiconductor die embedded therein, the semiconductor die coupled with a thermally-conductive element. The layered package includes, e.g., PCB boards with an intermediate layer having the semiconductor die arranged therein, and a pair of outer layers, with the thermally-conductive element including a thermally-conductive inlay in one of the outer layers.
    Type: Application
    Filed: August 11, 2017
    Publication date: July 5, 2018
    Inventor: Pierangelo MAGNI
  • Publication number: 20170125371
    Abstract: In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.
    Type: Application
    Filed: June 7, 2016
    Publication date: May 4, 2017
    Inventors: Pierangelo MAGNI, Alberto ARRIGONI
  • Publication number: 20160315059
    Abstract: An electronic component, such as an integrated circuit, includes one or more circuits with bumps extending in a longitudinal direction outward from the circuit. The bumps may be formed, e.g., by 3D printing, with at least one protrusion extending away from the longitudinal direction.
    Type: Application
    Filed: December 28, 2015
    Publication date: October 27, 2016
    Inventors: Paolo CREMA, Pierangelo MAGNI