Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for using an average reference voltage for sensing memory. An embodiment includes a memory having a plurality of memory cells coupled to a common node driver, where a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line, sense circuitry coupled to the different respective sense lines, and circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line.

Abstract: A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: The present disclosure includes apparatuses, methods, and systems for using an average reference voltage for sensing memory. An embodiment includes a memory having a plurality of memory cells coupled to a common node driver, where a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line, sense circuitry coupled to the different respective sense lines, and circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line.

Abstract: A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.