Patents by Inventor Pierre Joly

Pierre Joly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070170471
    Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 26, 2007
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-Pierre Joly, Olivier Faynot, Laurent Clavelier
  • Patent number: 7153747
    Abstract: A process for producing a MOS-type transistor includes providing a substrate comprising a thin layer of silicon (26), integral with an insulating support (14), and covered with a superficial layer (28) of a semi-conductor material, local etching of the superficial layer to expose the silicon layer in at least one channel region, formation of an insulated gate (50) above the silicon layer in the channel region, and formation of a source and a drain on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: December 26, 2006
    Assignee: Commissariat A L'Energie Atomique
    Inventor: Jean-Pierre Joly
  • Publication number: 20060252229
    Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 9, 2006
    Inventors: Jean-Pierre Joly, Laurent Ulmer, Guy Parat
  • Publication number: 20050258489
    Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 24, 2005
    Inventors: Jean-Pierre Joly, Michel Bruel, Claude Jaussaud
  • Publication number: 20050029594
    Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 10, 2005
    Inventors: Jean-Pierre Joly, Michel Bruel, Claude Jaussaud
  • Publication number: 20040180521
    Abstract: The present invention relates to process for producing a transistor of MOS type, comprising the following stages:
    Type: Application
    Filed: January 16, 2004
    Publication date: September 16, 2004
    Inventor: Jean-Pierre Joly
  • Patent number: 6782757
    Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising: a sensing element (4) integrating a membrane (8) in monocrystalline silicon carbide, made by micro-machining a substrate in polycrystalline silicon carbide, a first surface of membrane (8) intended to contact said medium, a second surface of membrane (8) comprising membrane deformation detection means (9) connected to electric contacts (10) to connect electric connection means (11), the surfaces of sensing element (4) contacting said medium being chemically inert to this medium; a carrier (5) to support sensing element (4) so that said first surface of membrane (8) may be contacted with said medium and the second surface of membrane (8) may be shielded from said medium, carrier (5) being in polycrystalline silicon carbide; a seal strip (6), in material containing silicon carbide, brazed between carrier (5) and sensing element (4) to protect the second surface of membra
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: August 31, 2004
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Fréderic Clerc, Claude Jaussaud, Jean-Pierre Joly, Jean Therme
  • Publication number: 20040079163
    Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising:
    Type: Application
    Filed: October 16, 2003
    Publication date: April 29, 2004
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-Frederic Clerc, Claude Jaussaud, Jean-Pierre Joly, Jean Therme
  • Patent number: 6688181
    Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising: a sensing element (4) integrating a membrane (8) in monocrystalline silicon carbide, made by micro-machining a substrate in polycrystalline silicon carbide, a first surface of membrane (8) intended to contact said medium, a second surface of membrane (8) comprising membrane deformation detection means (9) connected to electric contacts (10) to connect electric connection means (11), the surfaces of sensing element (4) contacting said medium being chemically inert to this medium; a carrier (5) to support sensing element (4) so that said first surface of membrane (8) may be contacted with said medium and the second surface of membrane (8) may be shielded from said medium, carrier (5) being in polycrystalline silicon carbide; a seal strip (6), in material containing silicon carbide, brazed between carrier (5) and sensing element (4) to protect the second surface of membra
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 10, 2004
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Fréderic Clerc, Claude Jaussaud, Jean-Pierre Joly, Jean Therme
  • Publication number: 20020089016
    Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.
    Type: Application
    Filed: March 11, 2002
    Publication date: July 11, 2002
    Inventors: Jean-Pierre Joly, Michel Bruel, Claude Jaussaud
  • Patent number: 6383972
    Abstract: A carbon fiber fabric having large specific surface area is made using a rayon precursor, and a catalyst is fixed on the fabric by impregnation or by cationic exchange. The carbon fiber fabric has pores with a mean size lying in the range 0.3 nm to 3 nm, a carbon content greater than 99%, and a high density of functional groups per unit area which favors the dispersion of metal catalyst in the form of fine particles and which is good for highly selective catalytic reactions in fine chemistry.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: May 7, 2002
    Assignee: Messier-Bugatti
    Inventors: Philippe Parmentier, Jean-Pierre Joly, Alain Perrard
  • Patent number: 6197695
    Abstract: This invention relates to a process for the manufacture of one electronic structure comprising at least one active component and at least one passive component or element on a support substrate made of an insulating material. A characteristic process comprises the following steps: make the active component in a surface layer made of semiconducting material from an initial substrate comprising a wafer of semiconducting material supporting the said surface layer, make electrical insulation areas capable of insulating the passive component or element from the active component, make the passive component or element on and/or in the electrical insulation areas, prepare the surface of the initial substrate face with the said electronic structure to make this face compatible for bonding with another substrate by molecular bonding, perform the bonding, the other substrate being the said support substrate made of an insulating material, eliminate all or part of the wafer of semiconducting material.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: March 6, 2001
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Joly, Bernard Aspar, Béatrice Biasse, Marc Zussy
  • Patent number: 6159323
    Abstract: Process for transfer of a microstructure (12) from an initial substrate (10) to a final substrate (32). The process includes the following steps in sequence:bonding between the initial substrate (10) and an intermediate substrate (24), the microstructure facing the intermediate substrate,formation of at least one layer (30) of bond material on at least one selected region (16) of the initial substrate including the microstructurebring the said selected region (16) into contact with the final substrate,treatment of the bond material in an area corresponding to the selected region (16), to increase the bond force,breaking the selected region (16) of the initial substrate, from the intermediate substrate (24).
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: December 12, 2000
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Joly, Gerard Nicolas, Michel Bruel
  • Patent number: 5373462
    Abstract: A process for producing an improved non-volatile storage cell of the metal-ferroelectric-semiconductor type is provided. The non-volatile storage cell has at least one metal-ferroelectric-semiconductor transistor formed in a semiconductor substrate and having a source (5), a drain (6), and a gate (4). The gate is insulated from the source and the drain by a ferroelectric layer (2). The transistor has at least one lateral programming electrode (BL) in contact with the ferroelectric layer and insulated from the gate. In a preferred embodiment the cell also has a dielectric layer (7) interposed between the ferroelectric layer and the substrate. Particular utility for the present invention is found in the area of static memory devices, although other utilities are contemplated.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: December 13, 1994
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Herve Achard, Jean-Pierre Joly
  • Patent number: 5232508
    Abstract: The invention relates to a gaseous phase chemical treatment reactor for wafers. The aim of the invention is to produce a reactor in which only the face of the wafer to be treated is in fact treated. This aim is achieved with the aid of a reactor comprising at least one treatment chamber (19) located within a main chamber (9) and connected by one of its ends to means (17) for injecting a treatment gas onto a wafer (1) and by its other end to a means (15) for securing said wafer, in that the latter is gripped between a heating susceptor or base (13) and the retaining means (15) in such a way as to seal said treatment chamber (19) and maintain within the latter a pressure below that of the main chamber (9). The invention more particularly relates to reactors for depositing tungsten on silicon wafers.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: August 3, 1993
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Chantal Arena, Jean-Pierre Joly, Patrice Noel, Michel Papapietro
  • Patent number: 5177350
    Abstract: An apparatus for electrically insulating viewing windows in an image intensifier tube is disclosed. The mechanical parts which are located close to the window are electrically insulated with the metal parts being held at a high voltage and electrically insulated on the outside of the image intensifier by an insulating screen. The insulating screen includes electrically conductive layer 36 and an insulating layer 37 which separates the metal parts 20, 26 from the conductive layer. The conductive layer also forms an equipotential layer which is opposite the metal parts and thereby "freezes" the distribution of the electrical lines of force in the insulating screen 35.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: January 5, 1993
    Assignee: Thomson Tubes Electroniques
    Inventors: Yves Beauvais, Pierre Joly, Jean-Marie Deon, Maurice Verat
  • Patent number: 4695641
    Abstract: Compounds of the formula: ##STR1## where R.sub.1 is alkyl having 1 or 2 carbon atoms,R.sub.2 is linear alkyl having 1 or 2, or from 12 to 16, carbon atoms,R.sub.3 and R.sub.4 are each chlorine or hydrogen, andX.sup.n.crclbar. is an anion, where n is the anion valence,with the proviso that R.sub.3 and R.sub.4 are not both hydrogen.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: September 22, 1987
    Assignee: Dollfus-Meig & Cie
    Inventors: Jean Saingier, Jean-Pierre A. Joly
  • Patent number: 4652267
    Abstract: Materials made of polyhydroxylated or polyaminated polymers can be rendered bacteriostatic or fungistatic by treating the materials with a solution of certain N-oxiranemethane N,N,N-trialkylammonium compounds in a base, and either spin drying the treated material and storing it protected from air for at least three hours, or drying the treated material and holding it at a temperature higher than 80.degree. C.
    Type: Grant
    Filed: April 11, 1983
    Date of Patent: March 24, 1987
    Assignee: Filature de La Gosse S.A.
    Inventors: Jean Saingier, Jean-Pierre A. Joly
  • Patent number: 4582917
    Abstract: Method for preparing N-oxiranemethane N,N,N-trialkylammonium compounds by reacting epichlorhydrin with a dialkylamine to form a hydroxy compound, cooling the hydroxy compound, increasing the concentration of hydroxy ions in the reaction mixture to form a compound of the formula ##STR1## and reacting this latter compound at room temperature in acetonitrile with a benzyl compound, for example benzyl bromide.
    Type: Grant
    Filed: April 30, 1984
    Date of Patent: April 15, 1986
    Assignee: Filature de la Gosse S.A.
    Inventors: Jean Saingier, Jean-Pierre A. Joly
  • Patent number: 4128795
    Abstract: A device is disclosed for damping the critical frequencies of a rotor suspended by a radial electromagnetic bearing which has means associated therewith for detecting the radial position of the rotor, comprising a servo-circuit for connection between the detecting means and windings of the electromagnetic bearing and including a circuit for controlling the current supply to the windings in response to signals from the detecting means to keep the rotor in a predetermined radial position. The servo-circuit is provided with means for the selective amplification of the phase advance gain of said circuit in a frequency equal to the speed of rotation of the rotor for damping said critical frequencies.
    Type: Grant
    Filed: December 17, 1976
    Date of Patent: December 5, 1978
    Assignee: Societe Europeene de Propulsion
    Inventors: Helmut Habermann, Maurice Brunet, Pierre Joly