Patents by Inventor Pierre Laurent
Pierre Laurent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200313218Abstract: A method of manufacturing by magnetron cathode sputtering an electrolyte film for use in solid oxide cells (SOC). This method comprises the steps consisting of heating a substrate to a temperature ranging from 200° C. to 1200° C.; followed by subjecting the substrate to at least two treatment cycles, each treatment cycle comprising: 1) depositing one layer of a metal precursor on the substrate by magnetron cathode sputtering of a target made up of the metal precursor, the sputtering being carried out under elemental sputtering conditions; followed by 2) oxidation-crystallisation of the metal precursor forming the layer deposited on the substrate in the presence of oxygen to obtain the transformation of the metal precursor into the electrolyte material; and in that the substrate is kept at a temperature ranging from 200° C. to 1200° C. for the entire duration of each treatment cycle.Type: ApplicationFiled: September 25, 2018Publication date: October 1, 2020Inventors: Julien Vulliet, Anne-Lise Thomann, Pierre-Laurent Coddet
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Patent number: 10606751Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.Type: GrantFiled: July 1, 2016Date of Patent: March 31, 2020Assignee: INTEL CORPORATIONInventors: Andrew Cunningham, Mark D. Gray, Alexander Leckey, Chris MacNamara, Stephen T. Palermo, Pierre Laurent, Niall D. McDonnell, Tomasz Kantecki, Patrick Fleming
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Patent number: 10567263Abstract: Technologies for simulating service degradation in telemetry data include a simulator device. The simulator device is to identify a telemetry data stream from a production system to a first management system. The simulator device is also to fork a copy of the telemetry data stream for transmission to a second management system, determine perturbations associated with a determined service degradation type, and apply the perturbations to the forked telemetry data stream. Other embodiments are also described and claimed.Type: GrantFiled: August 19, 2016Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Michael Hingston McLaughlin Bursell, Stephen T. Palermo, John J. Browne, Chris MacNamara, Pierre Laurent
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Publication number: 20190327190Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
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Patent number: 10455063Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key.Type: GrantFiled: August 15, 2017Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Cristian Florin F. Dumitrescu, Namakkal N. Venkatesan, Pierre Laurent, Bruce Richardson
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Patent number: 10400284Abstract: The present invention relates to a method for predicting whether a patient with a cancer is likely to respond to an epidermal growth factor receptor (EGFR) inhibitor, which method comprises determining the expression level hsa-miR-31-3p miRNA in a sample of said patient. The invention also relates to therapeutic uses of an EGFR inhibitor in a patient predicted to respond to said EGFR inhibitor.Type: GrantFiled: November 23, 2012Date of Patent: September 3, 2019Assignees: INTEGRAGEN, INSTITUT NATIONAL DE LA SANTE ET DE LA RECHERCHE MEDICALE (INSERM), CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), ASSISTANCE PUBLIQUE—HOPITAUX DE PARIS, UNIVERSITE PARIS DESCARTESInventors: Thomas Rio Frio, Pierre Laurent-Puig, Sandrine Imbeaud
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Patent number: 10372668Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.Type: GrantFiled: January 12, 2018Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T.J. O'Dwyer, Serge Zhilyaev
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Patent number: 10341264Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.Type: GrantFiled: June 30, 2016Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
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Patent number: 10294557Abstract: A steel part having a homogeneous multiphase microstructure in each region of the part, the microstructure containing ferrite, wherein the steel part is obtained by a process involving: cutting a blank from a strip of steel, having a specified composition; optionally, the blank undergoes prior cold deformation; the blank is heated to reach a soak temperature Ts above Ac1 but below Ac3 and held at this soak temperature Ts for a soak time ts adjusted so that the steel, after the blank has been heated, has an austenite content equal to or greater than 25% by area; the heated blank is transferred into a forming tool to hot-form the part; and the part is cooled within the tool at a cooling rate V such that the microstructure of the steel, after cooling the part, is a multiphase microstructure containing ferrite and being homogeneous in each region of the part.Type: GrantFiled: January 5, 2012Date of Patent: May 21, 2019Assignee: ArcelorMittal FranceInventors: Jacques Corquillet, Jacques Devroc, Jean-Louis Hochard, Jean-Pierre Laurent, Antoine Moulin, Nathalie Romanowski
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Publication number: 20190102312Abstract: A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.Type: ApplicationFiled: September 30, 2017Publication date: April 4, 2019Inventors: Niall D. McDonnell, Christopher MacNamara, John J. Browne, Andrew Cunningham, Brendan Ryan, Patrick Fleming, Namakkal N. Venkatesan, Bruce Richardson, Tomasz Kantecki, Sean Harte, Pierre Laurent
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Publication number: 20190086301Abstract: The invention relates to a method for counting cells, such as bacteria and/or somatic cells in liquid samples, such as in dairy products, preferably raw milk. Disclosed is a method comprising a combination of steps that apply dimeric nucleic acid dyes that normally do not penetrate cells (=cell-impermeant dyes), which are rendered cell-permeant by using the right combination of pH, buffer and temperature.Type: ApplicationFiled: March 17, 2017Publication date: March 21, 2019Inventors: Pierre Laurent EMOND, Nancy Gail PERLMUTTER, James Willis KREIDER
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Patent number: 10216483Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.Type: GrantFiled: September 5, 2017Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: T. J. O'Dwyer, Pierre Laurent
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Patent number: 10200410Abstract: A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust assessment ruleset to determine whether the system security controller is trusted/trustworthy. An untrusted system security controller peer device is replaced by another of the peer devices selected by the peer devices. The current system security controller peer device transfers system threat information and security risk information collected from the peer devices to the new system security controller elected by the peer devices.Type: GrantFiled: September 30, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Michael Hingston McLaughlin Bursell, Stephen T. Palermo, Chris MacNamara, Pierre Laurent, John J. Browne
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Patent number: 10199620Abstract: A system for attaching a thermal battery to a flange of a power supply section of an underwater craft, such as a torpedo, comprising a fixing sleeve arranged around and fixed to the battery and provided with fixing lugs comprising holes for the passage of screws for attachment to the flange, wherein the sleeve is in an overall shape of a C, of which an intermediate part and ends of branches comprise the fixing lugs for fixing the fixing sleeve to the flange.Type: GrantFiled: July 23, 2013Date of Patent: February 5, 2019Assignee: DCNSInventors: Jean-François Pierre Laurent Romand, Ludovic Madier
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Publication number: 20190007330Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: John J. Browne, Tomasz Kantecki, Chris Macnamara, Pierre Laurent, Sean Harte, Peter McCarthy, Jacqueline F. Jardim, Liang Ma
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Patent number: 10158578Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: GrantFiled: September 19, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Patent number: 10140458Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.Type: GrantFiled: April 7, 2016Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Chang Yong Kang, Pierre Laurent
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Publication number: 20180301243Abstract: The present invention relates to an integrated system for identifying cables and connected peripherals comprising at least one cable provided with at least one connector, at least one electronic chip associated with a powering to arrangement, the chip including at least one communication module with a terminal, a memory in which data, identification data of the cable, and at least one identifier are stored, said system being characterized in that it includes at least one antenna arranged along the cable and extending over at least one portion of the cable to be identified, said antenna being connected to the chip to allow data communication between said electronic chip and the communication terminal via activation of a management program contained in said chip.Type: ApplicationFiled: September 26, 2016Publication date: October 18, 2018Inventors: Pierre-Laurent POMMIER, Martin RADANLIEV, Julien ROUX
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Patent number: 10091122Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: GrantFiled: December 31, 2016Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Patent number: D854035Type: GrantFiled: July 17, 2017Date of Patent: July 16, 2019Assignee: Google LLCInventors: Ricardo Escutia, Bojana Duke, Heath Kessler, Pierre-Laurent Coirier, Joao Paulo Gil De Paiva