Patents by Inventor Pierre Laurent

Pierre Laurent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10158578
    Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
  • Patent number: 10140458
    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Chang Yong Kang, Pierre Laurent
  • Publication number: 20180301243
    Abstract: The present invention relates to an integrated system for identifying cables and connected peripherals comprising at least one cable provided with at least one connector, at least one electronic chip associated with a powering to arrangement, the chip including at least one communication module with a terminal, a memory in which data, identification data of the cable, and at least one identifier are stored, said system being characterized in that it includes at least one antenna arranged along the cable and extending over at least one portion of the cable to be identified, said antenna being connected to the chip to allow data communication between said electronic chip and the communication terminal via activation of a management program contained in said chip.
    Type: Application
    Filed: September 26, 2016
    Publication date: October 18, 2018
    Inventors: Pierre-Laurent POMMIER, Martin RADANLIEV, Julien ROUX
  • Patent number: 10091122
    Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
  • Publication number: 20180225255
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 9, 2018
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T.J. O'Dwyer, Serge Zhilyaev
  • Publication number: 20180183659
    Abstract: Examples include techniques for a configuration mechanism of a virtual switch. Example techniques include monitoring a database including parameter to configure a virtual switch at a computing platform hosting a plurality of virtual machines or containers. Changes to one or more parameters may cause changes in allocations of computing resources associated with supporting the virtual switch.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Inventors: Chris MacNamara, Mark D. Gray, Andrew Cunningham, Pierre Laurent
  • Publication number: 20180107453
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Application
    Filed: September 5, 2017
    Publication date: April 19, 2018
    Applicant: Intel Corporation
    Inventors: T.J. O'DWYER, PIERRE LAURENT
  • Publication number: 20180103129
    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key.
    Type: Application
    Filed: August 15, 2017
    Publication date: April 12, 2018
    Inventors: Cristian Florin F. Dumitrescu, Namakkal N. Venkatesan, Pierre Laurent, Bruce Richardson
  • Publication number: 20180097843
    Abstract: A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust assessment ruleset to determine whether the system security controller is trusted/trustworthy. An untrusted system security controller peer device is replaced by another of the peer devices selected by the peer devices. The current system security controller peer device transfers system threat information and security risk information collected from the peer devices to the new system security controller elected by the peer devices.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Applicant: INTEL CORPORATION
    Inventors: MICHAEL HINGSTON MCLAUGHLIN BURSELL, STEPHEN T. PALERMO, CHRIS MACNAMARA, PIERRE LAURENT, JOHN J. BROWNE
  • Publication number: 20180088977
    Abstract: Embodiments may be generally directed to techniques to cause communication of one or more packets from one or more network interfaces to one or more other network interfaces through a virtual machine monitor, determine at least one of latency and jitter for the virtual machine monitor based, at least in part, on each of the one or more packets communicated through the virtual machine monitor, and perform a corrective action when at least one of the latency and the jitter does not meet a requirement for a virtual machine on the virtual machine monitor.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: MARK GRAY, ANDREW CUNNINGHAM, CHRIS MACNAMARA, JOHN BROWNE, PIERRE LAURENT, ALEXANDER LECKEY
  • Publication number: 20180054379
    Abstract: Technologies for simulating service degradation in telemetry data include a simulator device. The simulator device is to identify a telemetry data stream from a production system to a first management system. The simulator device is also to fork a copy of the telemetry data stream for transmission to a second management system, determine perturbations associated with a determined service degradation type, and apply the perturbations to the forked telemetry data stream. Other embodiments are also described and claimed.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 22, 2018
    Inventors: Mike Bursell, Stephen T. Palermo, John J. Browne, Chris MacNamara, Pierre Laurent
  • Patent number: 9870339
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T. J. O'Dwyer, Serge Zhilyaev
  • Patent number: 9863568
    Abstract: This dampening device comprises a body defining a chamber and presenting at least one orifice intended for the inlet and the outlet of the fluid in the chamber. The dampening device further comprises i) a dampening member located in the chamber and comprising at least one foam with closed cells, and ii) a holding member configured to hold the dampening member in place. The dampening device being characterized in that at least one foam has a porosity comprised between 50% and 98%.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 9, 2018
    Assignee: MGI COUTIER
    Inventors: Marc Novellani, Peter Faulstroh, Pierre Laurent
  • Publication number: 20180004662
    Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: INTEL CORPORATION
    Inventors: ANDREW CUNNINGHAM, MARK D. GRAY, ALEXANDER LECKEY, CHRIS MACNAMARA, STEPHEN T. PALERMO, PIERRE LAURENT, NIALL D. MCDONNELL, TOMASZ KANTECKI, PATRICK FLEMING
  • Publication number: 20180006970
    Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
  • Publication number: 20170366477
    Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 21, 2017
    Inventors: John J. Browne, Seán Harte, Tomasz Kantecki, Pierre Laurent, Chris MacNamara
  • Publication number: 20170293765
    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Chang Yong Kang, Pierre Laurent
  • Patent number: 9778910
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: T. J. O'Dwyer, Pierre Laurent
  • Patent number: 9769290
    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Cristian Florin F. Dumitrescu, Namakkal N. Venkatesan, Pierre Laurent, Bruce Richardson
  • Patent number: 9753692
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: T. J. O'Dwyer, Pierre Laurent