Patents by Inventor Pietro Corona
Pietro Corona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9162876Abstract: Disclosed herein is a microelectromechanical device and a process for manufacturing same. One or more embodiments may include forming a semiconductor structural layer separated from a substrate by a dielectric layer, and opening a plurality of trenches through the structural layer exposing a portion of the dielectric layer. A sacrificial portion of the dielectric layer is selectively removed through the plurality of trenches in membrane regions so as to free a corresponding portion of the structural layer to form a membrane. To close the trenches, the wafer is brought to an annealing temperature for a time interval in such a way as to cause migration of the atoms of the membrane so as to reach a minimum energy configuration.Type: GrantFiled: March 13, 2012Date of Patent: October 20, 2015Assignee: STMicroelectronics S.r.l.Inventors: Pietro Corona, Marco Ferrera, Igor Varisco, Roberto Campedelli
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Patent number: 9105690Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.Type: GrantFiled: February 8, 2011Date of Patent: August 11, 2015Assignee: STMicroelectronics S.r.l.Inventors: Gabriele Barlocchi, Pietro Corona, Flavio Francesco Villa
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Patent number: 8575710Abstract: A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.Type: GrantFiled: April 13, 2012Date of Patent: November 5, 2013Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Gabriele Barlocchi, Pietro Corona, Benedetto Vigna, Lorenzo Baldo
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Patent number: 8420428Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.Type: GrantFiled: September 1, 2010Date of Patent: April 16, 2013Assignee: STMicroelectronics S.r.l.Inventors: Gabriele Barlocchi, Pietro Corona, Dino Faralli, Flavio Francesco Villa
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Patent number: 8344466Abstract: A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. Other embodiments are directed to MEMS devices and pressure sensors.Type: GrantFiled: August 4, 2010Date of Patent: January 1, 2013Assignee: STMicroelectronics S.r.l.Inventors: Pietro Corona, Stefano Losa, Ilaria Gelmi, Roberto Campedelli
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Patent number: 8334188Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.Type: GrantFiled: June 1, 2010Date of Patent: December 18, 2012Assignee: STMicroelectronics S.r.l.Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
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Publication number: 20120237061Abstract: Disclosed herein is a microelectromechanical device and a process for manufacturing same. One or more embodiments may include forming a semiconductor structural layer separated from a substrate by a dielectric layer, and opening a plurality of trenches through the structural layer exposing a portion of the dielectric layer. A sacrificial portion of the dielectric layer is selectively removed through the plurality of trenches in membrane regions so as to free a corresponding portion of the structural layer to form a membrane. To close the trenches, the wafer is brought to an annealing temperature for a time interval in such a way as to cause migration of the atoms of the membrane so as to reach a minimum energy configuration.Type: ApplicationFiled: March 13, 2012Publication date: September 20, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Pietro Corona, Marco Ferrera, Igor Varisco, Roberto Campedelli
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Publication number: 20120223402Abstract: A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.Type: ApplicationFiled: April 13, 2012Publication date: September 6, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Flavio Francesco Villa, Gabriele Barlocchi, Pietro Corona, Benedetto Vigna, Lorenzo Baldo
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Patent number: 8173513Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals.Type: GrantFiled: June 27, 2008Date of Patent: May 8, 2012Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Gabriele Barlocchi, Pietro Corona, Benedetto Vigna, Lorenzo Baldo
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Patent number: 8008738Abstract: An integrated differential pressure sensor includes, in a monolithic body of semiconductor material, a first face and a second face, a cavity extending at a distance from the first face and delimited therewith by a flexible membrane formed in part by epitaxial material from the monolithic body and in part by annealed epitaxial material from the monolithic body, an access passage in fluid communication with the cavity, and in the flexible membrane at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and is delimited at the second face with a portion of the monolithic body.Type: GrantFiled: June 29, 2010Date of Patent: August 30, 2011Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Pietro Corona, Gabriele Barlocchi, Lorenzo Baldo
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Publication number: 20110133186Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.Type: ApplicationFiled: February 8, 2011Publication date: June 9, 2011Applicant: STMICROELECTRONICS, S.R.L.Inventors: Gabriele BARLOCCHI, Pietro CORONA, Flavio Francesco VILLA
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Patent number: 7906406Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.Type: GrantFiled: July 17, 2007Date of Patent: March 15, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Gabriele Barlocchi, Pietro Corona, Flavio Francesco Villa
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Publication number: 20110031567Abstract: A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Pietro Corona, Stefano Losa, Ilaria Gelmi, Roberto Campedelli
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Patent number: 7871894Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.Type: GrantFiled: September 27, 2006Date of Patent: January 18, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Pietro Corona, Flavio Francesco Villa, Gabriele Barlocchi
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Publication number: 20100330721Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.Type: ApplicationFiled: September 1, 2010Publication date: December 30, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: GABRIELE BARLOCCHI, PIETRO CORONA, DINO FARALLI, FLAVIO FRANCESCO VILLA
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Patent number: 7846811Abstract: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.Type: GrantFiled: June 6, 2006Date of Patent: December 7, 2010Assignee: STMicroelectronics, S.r.l.Inventors: Flavio Francesco Villa, Pietro Corona, Gabriele Barlocchi
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Publication number: 20100269595Abstract: An integrated differential pressure sensor includes, in a monolithic body of semiconductor material, a first face and a second face, a cavity extending at a distance from the first face and delimited therewith by a flexible membrane formed in part by epitaxial material from the monolithic body and in part by annealed epitaxial material from the monolithic body, an access passage in fluid communication with the cavity, and in the flexible membrane at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and is delimited at the second face with a portion of the monolithic body.Type: ApplicationFiled: June 29, 2010Publication date: October 28, 2010Applicant: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Pietro Corona, Gabriele Barlocchi, Lorenzo Baldo
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Patent number: 7811848Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.Type: GrantFiled: July 12, 2006Date of Patent: October 12, 2010Assignee: STMicroelectronics S.R.L.Inventors: Gabriele Barlocchi, Pietro Corona, Dino Faralli, Flavio Francesco Villa
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Publication number: 20100237459Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: Flavio VILLA, Gabriele Barlocchi, Pietro Corona
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Patent number: 7763487Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.Type: GrantFiled: May 4, 2006Date of Patent: July 27, 2010Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Pietro Corona, Gabriele Barlocchi, Lorenzo Baldo