Patents by Inventor Pietro Corona

Pietro Corona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030168711
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: December 20, 2002
    Publication date: September 11, 2003
    Applicant: STMicroelectronics S.r.I.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20030148588
    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.
    Type: Application
    Filed: December 26, 2002
    Publication date: August 7, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20030129423
    Abstract: Method for manufacturing electromagnetic radiation reflecting devices, said method comprising the steps of: a) providing a silicon substrate defined by at least one first free surface, b) forming on said first surface a layer of protective material provided with an opening which exposes a region of the first free surface, and c)etching the region of the free surface by means of an anisotropic agent to remove at least one portion of the substrate and define a second free surface of the substrate inclined in relation to said first surface. Furthermore, said first free surface is parallel to the crystalline planes {110} of silicon substrate and said step (c) comprises a progressing step of the anisotropic agent such that the second free surface resulting from the etching step is parallel to the planes {100} of said substrate.
    Type: Application
    Filed: November 14, 2002
    Publication date: July 10, 2003
    Inventors: Ubaldo Mastromatteo, Pietro Corona, Flavio Villa, Gabriele Barlocchi
  • Patent number: 6376291
    Abstract: A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: April 23, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Flavio Villa, Pietro Corona
  • Patent number: 6362070
    Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: March 26, 2002
    Assignee: STMicroelectronics S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona