Abstract: An example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Abstract: An electrode assembly includes a first electrode; a second electrode; and a separator, the first electrode, the second electrode, and the separator wound about an axis defining a core and an outer circumference of the electrode assembly. The first electrode has a pair of first sides and a pair of second sides, a first portion extending between the pair of first sides, and a second portion extending between the pair of first sides, the first portion being coated with an active material, and at least a part of the second portion includes an electrode tab. The second portion includes a first part adjacent to the core of the electrode assembly, a second part adjacent to the outer circumference of the electrode assembly, and a third part between the first part and the second part. The first or second part has a smaller height than the third part.

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.

Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.