Patents by Inventor Pil-Kyu Kang

Pil-Kyu Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160013160
    Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.
    Type: Application
    Filed: July 10, 2015
    Publication date: January 14, 2016
    Inventors: Jin-ho CHUN, Pil-kyu Kang, Byung-Iyul Park, Jae-hwa Park, Ju-il Choi
  • Patent number: 9236349
    Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: January 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Ha Lee, Pil-Kyu Kang, Tae-Yeong Kim, Ho-Jin Lee, Byung-Lyul Park, Gil-Heyun Choi
  • Patent number: 9171753
    Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: October 27, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin Lee, Kyu-ha Lee, Gilheyun Choi, YongSoon Choi, Pil-Kyu Kang, Byung-Lyul Park, Hyunsoo Chung
  • Publication number: 20150279825
    Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 1, 2015
    Inventors: Pil-Kyu KANG, Byung Lyul PARK, Taeyeong KIM, Yeun-Sang PARK, Dosun LEE, Ho-Jin LEE, Jinho CHUN, Ju-il CHOI, Yi Koan HONG
  • Publication number: 20150243637
    Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Inventors: Pil-Kyu Kang, Taeyeong Kim, Byung Lyul Park, Jumyong Park, Jinho Park, Kyu-Ha Lee, Deok-Young Jung, Gilheyun Choi
  • Patent number: 9103974
    Abstract: Semiconductor devices having an optical transceiver include a cladding on a substrate, a protrusion vertically extending trough the cladding and materially in continuity with the substrate, and a coupler on the cladding and the protrusion.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 11, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-Kyu Kang, Dae-Lok Bae, Byung-Lyul Park, Gil-Heyun Choi
  • Patent number: 9070748
    Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-Kyu Kang, Taeyeong Kim, Byung Lyul Park, Jumyong Park, Jinho Park, Kyu-Ha Lee, Deok-Young Jung, Gilheyun Choi
  • Patent number: 9064941
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok-young Jung, Pil-kyu Kang, Byung-lyul Park, Ji-soon Park, Seong-min Son, Jin-ho An, Ji-hwang Kim
  • Publication number: 20150155233
    Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.
    Type: Application
    Filed: September 19, 2014
    Publication date: June 4, 2015
    Inventors: Kyu-Hee Han, Pil-Kyu Kang, Taejin Yim, Naein Lee
  • Publication number: 20150137326
    Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 21, 2015
    Inventors: Pil-Kyu KANG, Byung Lyul PARK, SungHee KANG, TAESEONG KIM, TAEYEONG KIM, KWANGJIN MOON, Jae-Hwa PARK, SUKCHUL BANG, Seongmin SON, JIN HO AN, Ho-Jin LEE, JEONGGI JIN
  • Publication number: 20150132950
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Deok-young JUNG, Pil-kyu KANG, Byung-lyul PARK, Ji-soon PARK, Seong-min SON, Jin-ho AN, Ji-hwang KIM
  • Publication number: 20150093896
    Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Kyu-Ha Lee, Ho-Jin Lee, Pil-Kyu Kang, Byung Lyul Park, Hyunsoo Chung, Gilheyun Choi
  • Patent number: 8963336
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-young Jung, Pil-kyu Kang, Byung-lyul Park, Ji-soon Park, Seong-min Son, Jin-ho An, Ji-hwang Kim
  • Patent number: 8952543
    Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Byung-Lyul Park, Hyun-Soo Chung, Gil-Heyun Choi
  • Patent number: 8941216
    Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Ha Lee, Ho-Jin Lee, Pil-Kyu Kang, Byung Lyul Park, Hyunsoo Chung, Gilheyun Choi
  • Patent number: 8927426
    Abstract: Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Gilheyun Choi, YongSoon Choi, Byung Lyul Park, Hyunsoo Chung
  • Patent number: 8901694
    Abstract: An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Joong-Han Shin, Byung-Lyul Park, Gil-Heyun Choi
  • Publication number: 20140327150
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Deok-young JUNG, Pil-kyu KANG, Byung-lyul PARK, Ji-soon PARK, Seong-min SON, Jin-ho AN, Ji-hwang KIM
  • Patent number: 8873901
    Abstract: Optical input/output (I/O) devices, which include a substrate including a trench, a waveguide within the trench of the substrate; and a photodetector within the trench and optically connected to the waveguide. An upper surface of the photodetector is at a same level as an upper surface of the waveguide.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Dae-Lok Bae, Byung-Lyul Park, Gil-Heyun Choi
  • Patent number: 8866187
    Abstract: A photodetector structure can include a silicon substrate and a silicon layer on the silicon substrate, that can include a first portion of an optical transmission medium that further includes a silicon cross-sectional transmission face. A germanium layer can be on the silicon substrate and can include a second portion of the optical transmission medium, adjacent to the first portion can include a germanium cross-sectional transmission face butt-coupled to the silicon cross-sectional transmission face.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Won Na, Pil-Kyu Kang, Seong Gu Kim, Yong Hwack Shin, Ho-Chul Ji, Jung Hyung Pyo, Kyoung Ho Ha