Patents by Inventor Pil-Soon Hong

Pil-Soon Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160202520
    Abstract: A display device may include the following elements: a first transistor including a gate electrode, a source electrode, and drain electrode; a gate line electrically connected to the gate electrode; a data line electrically connected to the source electrode; a common electrode; a passivation layer overlapping the common electrode; a first pixel electrode electrically connected to the drain electrode and positioned between the common electrode and the passivation layer; a first liquid crystal layer, which is positioned between the common electrode and the first pixel electrode; a second transistor electrically connected to the gate line; a second pixel electrode electrically connected to the second transistor; a second liquid crystal layer positioned between the common electrode and the second pixel electrode; and a supporting member positioned between the common electrode and the passivation layer and positioned between the first liquid crystal layer and the second liquid crystal layer.
    Type: Application
    Filed: October 1, 2015
    Publication date: July 14, 2016
    Inventors: Pil Soon HONG, Gwui-Hyun PARK, Jin Ho JU
  • Publication number: 20160195746
    Abstract: A thin film transistor array panel includes: a gate line and a data line on a substrate, insulatively crossing each other; a thin film transistor connected to the gate line and to the data line; a first color filter overlapping the thin film transistor; a second color filter overlapping the first color filter; a passivation layer covering the first color filter and the second color filter; a first pixel electrode on the passivation layer, the first pixel electrode overlapping the first color filter and the second color filter; and a second pixel electrode on the first pixel electrode, the second pixel electrode overlapping the first color filter and the second color filter and connected with a drain electrode of the thin film transistor.
    Type: Application
    Filed: June 16, 2015
    Publication date: July 7, 2016
    Inventors: Pil Soon HONG, Gwui-Hyun PARK
  • Publication number: 20160148955
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention has a first gate insulting layer and a second gate insulating layer disposed on the first gate insulating layer. The gate electrode of the present invention is formed in an opening of the first gate insulating layer with the same height as that of the gate electrode. Therefore, the second gate insulating layer formed on the gate electrode and the first gate insulating layer renders a flat surface without a step. This may reduce or eliminate any defects caused by the step around gate electrodes, such as source electrode and/or drain electrode cracks.
    Type: Application
    Filed: April 30, 2015
    Publication date: May 26, 2016
    Inventors: Pil Soon Hong, Gwui-Hyun Park, Jin Ho Ju
  • Publication number: 20150253601
    Abstract: A method of manufacturing a liquid crystal display panel. The method includes: preparing a substrate; forming a sacrificial pattern including a negative photoresist material on the substrate; forming a loop portion to cover top and side surfaces of the sacrificial pattern and to expose one side surface of the sacrificial pattern; forming a cavity defined as a predetermined region in the loop portion by performing a strip process on the exposed side surface of the sacrificial pattern by using (utilizing) a strip solution and removing the sacrificial pattern; forming a liquid crystal layer by injecting liquid crystal in the cavity; and forming a blocking member to cover a surface of the cavity into which the liquid crystal is injected.
    Type: Application
    Filed: October 6, 2014
    Publication date: September 10, 2015
    Inventors: Pil-Soon Hong, Gwui-Hyun Park, Jin-Ho Ju
  • Publication number: 20150198840
    Abstract: A liquid crystal display is provided. The liquid crystal display includes: a substrate; a thin film transistor; a pixel electrode; a roof layer; a plurality of microcavities; and a partition wall. The thin film transistor is disposed on the substrate. The pixel electrode is disposed on the thin film transistor. The roof layer faces the pixel electrode. The microcavities are between the pixel electrode and the roof layer, the microcavities include a liquid crystal material. The partition wall is between the microcavities, and the partition wall is perpendicular to the roof layer.
    Type: Application
    Filed: June 18, 2014
    Publication date: July 16, 2015
    Inventors: Yang-Ho JUNG, Pil Soon HONG, Jun Hong PARK, Seung Bo SHIM, Jin Ho JU
  • Patent number: 9041001
    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Pil Soon Hong, Gwui-Hyun Park, Jin-Su Byun, Sang Gab Kim
  • Publication number: 20150053984
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Inventors: JEAN-HO SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Patent number: 8927189
    Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwui-Hyun Park, Pil Soon Hong, Jinho Ju, Taegyun Kim, Jin-Su Byun, Dong Min Kim, Seung Ki Kim, Doo Youn Lee
  • Patent number: 8865528
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 21, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Publication number: 20140242515
    Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.
    Type: Application
    Filed: August 7, 2013
    Publication date: August 28, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwui-Hyun PARK, Pil Soon HONG, Jinho JU, Taegyun KIM, Jin-Su BYUN, Dong Min KIM, Seung Ki KIM, Doo Youn LEE
  • Publication number: 20140124786
    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Pil Soon HONG, Gwui-Hyun PARK, Jin-Su BYUN, Sang Gab KIM
  • Patent number: 8653530
    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil Soon Hong, Gwui-Hyun Park, Jin-Su Byun, Sang Gab Kim
  • Patent number: 8557620
    Abstract: Provided is a method of manufacturing a display substrate. In the method, a gate line, a data line crossing the gate line, and a switching device are formed on a base substrate. A passivation layer, a first resist layer and a second resist layer are formed on the base substrate. The first resist layer and the second resist layer are patterned to form a resist pattern and an etch-stop pattern, the etch-stop pattern having a sidewall protruding from a sidewall of the resist pattern. A portion of the passivation layer is removed to form a contact hole on a drain electrode of the switching device. A pixel electrode electrically connected to the switching device through the contact hole is formed. Thus, an undercut between an etch-stop pattern and a resist pattern may be more easily formed without over-etching a passivation layer.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 15, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Soon Hong, Jung-In Park, Hi-Kuk Lee
  • Patent number: 8450160
    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil Soon Hong, Gwui-Hyun Park, Sang Gab Kim
  • Publication number: 20130087800
    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
    Type: Application
    Filed: March 19, 2012
    Publication date: April 11, 2013
    Inventors: Pil Soon HONG, Gwui-Hyun Park, Jin-Su Byun, Sang Gab Kim
  • Publication number: 20120149158
    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.
    Type: Application
    Filed: March 29, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Soon HONG, Gwui-Hyun PARK, Sang Gab KIM
  • Publication number: 20110269309
    Abstract: Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: wherein R is one of hydrogen, an alkyl having 1 to 10 carbon atoms, a cycloalkyl having 4 to 8 carbon atoms, and a phenyl group.
    Type: Application
    Filed: December 29, 2010
    Publication date: November 3, 2011
    Applicants: DONGWOO FINE-CHEM CO., LTD, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-Soon HONG, Gwui-Hyun PARK, Jin-Ho JU, Jean-Ho SONG, Sang-Tae KIM, Seong-Hyeon KIM, Won-Young CHANG, Jong-Heum YOON, Eun-Sang LEE, Min-Ju IM
  • Publication number: 20110133193
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Application
    Filed: July 27, 2010
    Publication date: June 9, 2011
    Inventors: Jean-Ho SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Patent number: 7781345
    Abstract: In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Pil-Soon Hong
  • Publication number: 20100055851
    Abstract: The present invention relates to a photoresist composition that comprises a resin that is represented by Formula 1, a method for forming a thin film pattern, and a method for manufacturing a thin film transistor array panel by using the same. Herein, R is a methylene group, and n is an integer of 1 or more.
    Type: Application
    Filed: February 19, 2009
    Publication date: March 4, 2010
    Applicants: Samsung Electronics Co., Ltd., AZ Electronic Materials (Japan) K.K.
    Inventors: Hi-Kuk Lee, Sang-Hyun Yun, Jung-In Park, Woo-Seok Jeon, Pil-Soon Hong, Doek-Man Kang, Sae-Tae Oh, Chang-Ik Lee