Abstract: A method of manufacturing a liquid crystal display panel. The method includes: preparing a substrate; forming a sacrificial pattern including a negative photoresist material on the substrate; forming a loop portion to cover top and side surfaces of the sacrificial pattern and to expose one side surface of the sacrificial pattern; forming a cavity defined as a predetermined region in the loop portion by performing a strip process on the exposed side surface of the sacrificial pattern by using (utilizing) a strip solution and removing the sacrificial pattern; forming a liquid crystal layer by injecting liquid crystal in the cavity; and forming a blocking member to cover a surface of the cavity into which the liquid crystal is injected.

Abstract: A liquid crystal display is provided. The liquid crystal display includes: a substrate; a thin film transistor; a pixel electrode; a roof layer; a plurality of microcavities; and a partition wall. The thin film transistor is disposed on the substrate. The pixel electrode is disposed on the thin film transistor. The roof layer faces the pixel electrode. The microcavities are between the pixel electrode and the roof layer, the microcavities include a liquid crystal material. The partition wall is between the microcavities, and the partition wall is perpendicular to the roof layer.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: Provided is a method of manufacturing a display substrate. In the method, a gate line, a data line crossing the gate line, and a switching device are formed on a base substrate. A passivation layer, a first resist layer and a second resist layer are formed on the base substrate. The first resist layer and the second resist layer are patterned to form a resist pattern and an etch-stop pattern, the etch-stop pattern having a sidewall protruding from a sidewall of the resist pattern. A portion of the passivation layer is removed to form a contact hole on a drain electrode of the switching device. A pixel electrode electrically connected to the switching device through the contact hole is formed. Thus, an undercut between an etch-stop pattern and a resist pattern may be more easily formed without over-etching a passivation layer.

Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.

Abstract: Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: wherein R is one of hydrogen, an alkyl having 1 to 10 carbon atoms, a cycloalkyl having 4 to 8 carbon atoms, and a phenyl group.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed.

Abstract: The present invention relates to a photoresist composition that comprises a resin that is represented by Formula 1, a method for forming a thin film pattern, and a method for manufacturing a thin film transistor array panel by using the same. Herein, R is a methylene group, and n is an integer of 1 or more.

Abstract: In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed.

Abstract: Provided is a method of manufacturing a display substrate. In the method, a gate line, a data line crossing the gate line, and a switching device are formed on a base substrate. A passivation layer, a first resist layer and a second resist layer are formed on the base substrate. The first resist layer and the second resist layer are patterned to form a resist pattern and an etch-stop pattern, the etch-stop pattern having a sidewall protruding from a sidewall of the resist pattern. A portion of the passivation layer is removed to form a contact hole on a drain electrode of the switching device. A pixel electrode electrically connected to the switching device through the contact hole is formed. Thus, an undercut between an etch-stop pattern and a resist pattern may be more easily formed without over-etching a passivation layer.