Patents by Inventor Pin Chia Su
Pin Chia Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8416555Abstract: A system for chucking and de-chucking a work piece comprises a wafer stage having a chuck support for supporting a chuck. The wafer stage further comprises a chuck mounted on the chuck support for receiving and attaching the work piece thereto; a support lift means for supporting the work piece; a driving means coupled to the support lift means for gradually raising the support lift means to contact the work piece in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.Type: GrantFiled: July 25, 2011Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Tsung Lu, Pin-Chia Su, Yu-Chih Liou
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Publication number: 20110310525Abstract: A system for chucking and de-chucking a work piece comprises a wafer stage having a chuck support for supporting a chuck. The wafer stage further comprises a chuck mounted on the chuck support for receiving and attaching the work piece thereto; a support lift means for supporting the work piece; a driving means coupled to the support lift means for gradually raising the support lift means to contact the work piece in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.Type: ApplicationFiled: July 25, 2011Publication date: December 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Tsung Lu, Pin-Chia Su, Yu-Chih Liou
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Patent number: 8049213Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.Type: GrantFiled: December 18, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chung Su, Yi-Wei Chiu, Tzu Chan Weng, Yih Song Chiu, Pin Chia Su, Chih-Cherng Jeng, Kuo-Hsiu Wei
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Publication number: 20110223767Abstract: A method of recycling a control wafer having a low-k dielectric layer deposited thereon involves etching a portion of the low-k dielectric layer using a plasma resulting in a residual film of the low-k dielectric layer and byproduct particulates of carbon on the substrate. The residual dielectric film is removed by wet etching with a low polarization organic solvent that includes HF and a surfactant.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Lin Liang, Yu-Sheng Su, Tai-Yung Yu, Perre Kao, Pin Chia Su, Li Te Hsu
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Patent number: 8000081Abstract: A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a sensor attached to the driving means for detecting a change in the variable quantity; and a controller for controlling the variable quantity to the driving means when a predetermined variable quantity is detected in comparison to the change in the variable quantity for a predetermined time.Type: GrantFiled: July 14, 2008Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Tsung Lu, Pin-Chia Su, Yu-Chih Liou
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Patent number: 7995323Abstract: A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.Type: GrantFiled: July 14, 2008Date of Patent: August 9, 2011Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., Lam ResearchInventors: Chung-Tsung Lu, Pin-Chia Su, Yu-Chih Liou
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Patent number: 7973293Abstract: A method comprises supplying a dopant gas in an arc chamber of an ion source. A dilutant is supplied to dilute the dopant gas. The dilutant comprises about 98.5 wt. % xenon and about 1.5 wt. % hydrogen. An ion beam is generated from the diluted dopant gas using the ion source.Type: GrantFiled: April 1, 2009Date of Patent: July 5, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Peng Lin, Wei-Ming You, Ruey-Yong Deng, Jiunn-Nan Lin, Sheng-Chien Tung, Pin Chia Su
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Patent number: 7910014Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.Type: GrantFiled: December 21, 2007Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li Te Hsu, Jin Lin Liang, Shih Cheng Yeh, Pin Chia Su
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Publication number: 20110062375Abstract: An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Patent number: 7851374Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.Type: GrantFiled: October 31, 2007Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20100176306Abstract: A method comprises supplying a dopant gas in an arc chamber of an ion source. A dilutant is supplied to dilute the dopant gas. The dilutant comprises about 98.5 wt. % xenon and about 1.5 wt. % hydrogen. An ion beam is generated from the diluted dopant gas using the ion source.Type: ApplicationFiled: April 1, 2009Publication date: July 15, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Peng LIN, Wei-Ming YOU, Ruey-Yong DENG, Jiunn-Nan LIN, Sheng-Chien TUNG, Pin Chia SU
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Publication number: 20100008013Abstract: A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a sensor attached to the driving means for detecting a change in the variable quantity; and a controller for controlling the variable quantity to the driving means when a predetermined variable quantity is detected in comparison to the change in the variable quantity for a predetermined time.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Tsung LU, Pin-Chia SU, Yu-Chih LIOU
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Publication number: 20100008014Abstract: A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., LAM RESEARCHInventors: Chung-Tsung LU, Pin-Chia SU, Yu-Chih LIOU
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Publication number: 20090233447Abstract: A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The combination of the dry and wet etching provides effective removal of the dielectric material without damaging the wafer substrate and any residual wet etching byproduct particulate remaining on the wafer substrate is then removed by APM cleaning and scrubbing.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Lin Liang, Yu-Sheng Su, Tai-Yung Yu, Perre Kao, Pin-Chia Su, Li Te Hsu
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Patent number: 7588946Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.Type: GrantFiled: July 25, 2005Date of Patent: September 15, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Tsung Tso, Jiun-Hong Lai, Mei-Jen Wu, Li Te Hsu, Pin Chia Su, Po-Zen Chen
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Publication number: 20090152545Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Chung Su, Yi-Wei Chiu, Tzu-Chan Weng, Yih Song Chiu, Pin Chia Su, Chih-Cherng Jeng, Kuo-Hsiu Wei
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Publication number: 20090111269Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20090087929Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.Type: ApplicationFiled: December 21, 2007Publication date: April 2, 2009Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li Te Hsu, Jin Lin Liang, Shih Cheng Yeh, Pin Chia Su
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Patent number: 7306746Abstract: A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.Type: GrantFiled: January 30, 2004Date of Patent: December 11, 2007Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Fang-Cheng Chen, Li Te Hsu, I Cheng Tseng, Hsu Chiung Wen, Tsung Chuan Chen, Pin Chia Su
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Patent number: 7101748Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region.Type: GrantFiled: February 26, 2004Date of Patent: September 5, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Lung Yeh, Chu-We Hu, Li-Te Hsu, Pin-Chia Su