Patents by Inventor Pin Chia Su

Pin Chia Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7018928
    Abstract: A method for reducing the loss of silicon in a plasma assisted photoresist etching process including providing a silicon substrate including a polysilicon gate structure; masking a portion of the silicon substrate with photoresist to carry out an ion implantation process for forming source and drain regions; carrying out an ion implantation process; and, removing the photoresist according to at least one plasma assisted process wherein the at least one plasma assisted process comprises fluorine containing, oxygen, and hydrogen containing plasma source gases.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: March 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li Te Hsu, Chia Lun Chen, Chiang Jen Peng, Pin Chia Su
  • Publication number: 20050191802
    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Yu-Lung Yeh, Chu-We Hu, Li-Te Hsu, Pin-Chia Su
  • Publication number: 20050054209
    Abstract: A method for reducing the loss of silicon in a plasma assisted photoresist etching process including providing a silicon substrate including a polysilicon gate structure; masking a portion of the silicon substrate with photoresist to carry out an ion implantation process for forming source and drain regions; carrying out an ion implantation process; and, removing the photoresist according to at least one plasma assisted process wherein the at least one plasma assisted process comprises fluorine containing, oxygen, and hydrogen containing plasma source gases.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Inventors: Li Te Hsu, Chia Lun Chen, Chiang Jen Peng, Pin Chia Su
  • Patent number: 6808589
    Abstract: A wafer transfer robot for a wafer processing system, such as a wet bench system, and a method for utilizing the robot. The wafer transfer robot can be constructed by a robot arm that is equipped with a plurality of wafer blades each adapted for picking-up and carrying one of a plurality of wafers. The plurality of wafer blades each has a predetermined thickness, a top surface, a bottom surface and a predetermined spacing from adjacent wafer blades. A plurality of sensors, such as optical sensors, capacitance sensors or magnetic sensors, with at least one mounted on the bottom side of one of the plurality of wafer blades for sensing the presence of metal on a wafer carried on an adjacent wafer blade immediately below the one of the plurality of wafer blades.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: October 26, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd
    Inventors: Yu-Sheng Su, Chiang-Jen Peng, Pin-Chia Su, Wen-Lang Wu
  • Patent number: 6777334
    Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Le Der Shiu, Pin Chia Su, Yin Shen Chu
  • Publication number: 20040018732
    Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 29, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Le Der Shiu, Pin Chia Su, Yin Shen Chu
  • Publication number: 20030230384
    Abstract: A wafer transfer robot for a wafer processing system, such as a wet bench system, and a method for utilizing the robot. The wafer transfer robot can be constructed by a robot arm that is equipped with a plurality of wafer blades each adapted for picking-up and carrying one of a plurality of wafers. The plurality of wafer blades each has a predetermined thickness, a top surface, a bottom surface and a predetermined spacing from adjacent wafer blades. A plurality of sensors, such as optical sensors, capacitance sensors or magnetic sensors, with at least one mounted on the bottom side of one of the plurality of wafer blades for sensing the presence of metal on a wafer carried on an adjacent wafer blade immediately below the one of the plurality of wafer blades.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 18, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Sheng Su, Chiang-Jen Peng, Pin-Chia Su, Wen-Lang Wu