Patents by Inventor PIN HU
PIN HU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130092935Abstract: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.Type: ApplicationFiled: October 12, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Wang, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Hsien-Pin Hu, Wei-Cheng Wu, Li-Han Hsu, Meng-Han Lee
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Patent number: 8362591Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.Type: GrantFiled: June 8, 2010Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Tsung Yen, Hsien-Pin Hu, Jhe-Ching Lu, Chin-Wei Kuo, Ming-Fa Chen, Sally Liu
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Publication number: 20130009317Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.Type: ApplicationFiled: July 7, 2011Publication date: January 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Chun HSIEH, Wei-Cheng WU, Hsiao-Tsung YEN, Hsien-Pin HU, Shang-Yun HOU, Shin-Puu JENG
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Publication number: 20120305916Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: ApplicationFiled: August 4, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 8319349Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: GrantFiled: January 3, 2012Date of Patent: November 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
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Publication number: 20120238057Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
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Publication number: 20120206160Abstract: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 ?m. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Cheng WU, Hsien-Pin HU, Shang-Yun HOU, Shin-Puu JENG, Chen-Hua YU, Chao-Hsiang YANG
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Publication number: 20120104578Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: ApplicationFiled: January 3, 2012Publication date: May 3, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hu Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
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Publication number: 20120061795Abstract: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.Type: ApplicationFiled: September 9, 2010Publication date: March 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Hsien-Pin Hu, Chin-Wei Kuo, Sally Liu
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Publication number: 20120049322Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.Type: ApplicationFiled: September 1, 2010Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Wei-Chih Chiou, Shin-Puu Jeng
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Patent number: 8105875Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: GrantFiled: October 14, 2010Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
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Publication number: 20110298551Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiao-Tsung YEN, Hsien-Pin HU, Jhe-Ching LU, Chin-Wei KUO, Ming-Fa CHEN, Sally LIU
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Publication number: 20110291232Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Hsien-Pin Hu, Sally Liu, Ming-Fa Chen, Jhe-Ching Lu
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Publication number: 20110193221Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.Type: ApplicationFiled: May 5, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
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Publication number: 20110193235Abstract: A device is formed to include an interposer having a top surface, and a bump on the top surface of the interposer. An opening extends from the top surface into the interposer. A first die is bonded to the bump. A second die is located in the opening of the interposer and bonded to the first die.Type: ApplicationFiled: May 6, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Jiun Ren Lai, Ming-Fa Chen
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Patent number: 7117460Abstract: A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.Type: GrantFiled: March 4, 2004Date of Patent: October 3, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shou-Zen Chang, Wei-Ming Chen, Hsien-Pin Hu, Chia-Nan Lee
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Publication number: 20050198603Abstract: A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.Type: ApplicationFiled: March 4, 2004Publication date: September 8, 2005Inventors: Shou-Zen Chang, Wei-Ming Chen, Hsien-Pin Hu, Chia-Nan Lee
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Publication number: 20030041794Abstract: A cooling system comprises: a plurality of inhaling devices that are installed in the circuit-board room and connected with a plurality of ventholes the air between the plurality of circuit boards in the circuit-board room; a power generator is connected with the plurality of inhaling devices to supply the power into the cooling system, wherein the power generator can not affect the operation of the surfscan apparatus.Type: ApplicationFiled: September 5, 2001Publication date: March 6, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chi-Pin Hu, Jui-Yen Liu
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Patent number: 5269931Abstract: Cationic charged semihydrophobic polyethersulfone (CSfIP) membranes having hydrophilic and semihydrophobic properties are provided, as well as preparation of the same by post-treatment. Typically, as an illustration, a microporous hydrophilic polyethersulfone membrane substrate which contains non-leachable polymeric additive having functional groups is treated in an alkaline solution for simultaneous or sequential reaction with 1) a primary charge modifying agent which is an epichlorohydrin modified polyamine, and 2) a secondary polymeric charge modifying agent containing a positive charge (or for reaction with the primary charge modifying agent alone); then baked until cured at elevated temperature; and finally washed and dried. The CSHP membranes are used in various applications such as the filtration of fluids and the macromolecular transfer of biomolecules either from electrophoresis gels or directly to immobilization on the membrane for hybridization and stripping.Type: GrantFiled: August 20, 1991Date of Patent: December 14, 1993Assignee: Gelman Sciences Inc.Inventors: Ho-Pin Hu, Inessa Katsnelson, Alan Sellinger, Wesley Tamashiro
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Patent number: 5151189Abstract: Cationic charge modified microporous hydrophilic membranes are provided, as well as preparation of the same by post-treatment. Typically, as an illustration, a microporous hydrophilic membrane substrate which contains non-leachable polymeric additive having functional groups is treated in an alkaline solution for simultaneous or sequential reaction with 1) a primary charge modifying agent which is an epichlorohydrin modified polyamine, and 2) a secondary polymeric charge modifying agent containing a fixed formal positive charge (or for reaction with the primary charge modifying agent alone); then cured at elevated temperature; and finally washed and dried. The cationically charged microporous membranes are used in various applications such as the filtration of fluids and the macromolecular transfer from electrophoresis gels.Type: GrantFiled: September 17, 1990Date of Patent: September 29, 1992Assignee: Gelman Sciences, Inc.Inventors: Ho-Pin Hu, Inessa Katsnelson, Alan Sellinger