Abstract: A reflective display panel includes a first substrate, a second substrate, pixel structures, spacers, a first alignment layer, a second alignment layer, a liquid crystal layer, and light shielding patterns. The pixel structures are disposed on the first substrate. The spacers and the liquid crystal layer are disposed between the first and second substrates. The first alignment layer is disposed on the first substrate and has a first alignment direction. The second alignment layer is disposed on the second substrate and has a second alignment direction. Each spacer has a first side edge and a second side edge facing away from each other and sequentially arranged along the first or second alignment direction. In a stacking direction of the first and second substrates, each light shielding pattern overlaps with the second side edge of one of the spacers, but does not overlap with the first side edge thereof.

Abstract: A vehicle device includes a heat sink, a retaining wall, at least one electronic component, a fan and an upper cover. The heat sink has a drainage portion and an electronic component accommodating portion, in which the drainage portion has a fan accommodating portion. The retaining wall isolates the drainage portion and the electronic component accommodating portion. The at least one electronic component is disposed over the electronic component accommodating portion. The fan is disposed over the fan accommodating portion. The upper cover covers the heat sink, the retaining wall, the at least one electronic component and the fan, and has through holes and at least one first drain outlet, in which the through holes are aligned with the drainage portion, and the at least one first drain outlet is adjacent to an edge portion of the drainage portion and away from the fan.

Abstract: A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.

Abstract: A method of manufacturing an integrated circuit (IC) includes providing a structure having a fin over a substrate in a region of the IC, a sacrificial gate stack engaging a channel region of the fin, and gate spacers on sidewalls of the sacrificial gate stack. The first layers and the second layers are alternately stacked over the substrate. The method also includes etching the fin adjacent the gate spacers, resulting in source/drain trenches, partially recessing the second layers exposed in the source/drain trenches, resulting in gaps between adjacent layers of the first layers in the fin, depositing inner spacer features in the gaps in the fin, epitaxially growing source/drain features in the source/drain trenches, and replacing the sacrificial gate stack with a metal gate stack. The metal gate stack includes a gate dielectric layer disposed over top and sidewalls of the fin having both the first and the second layers.

Abstract: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: An accuracy measurement method of an autonomous mobile vehicle, a calculating device, and an autonomous mobile vehicle are provided. The accuracy measurement method includes a distance calculating step, a regression center calculating step, and an average calculating step. The distance calculating step includes a controlling step, a light beam emitting step, an image capturing step, an image analyzing step, and a converting step. The regression center calculating step is performed after the distance calculating step is repeatedly performed by at least two times. The accuracy measurement method is performed to obtain an X-axis offset in an X-axis direction, a Y-axis offset in a Y-axis direction, and an angle deflection of an autonomous mobile vehicle.

Abstract: Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Abstract: A character concealable keycap module includes a first cap structure, a light covering layer, and a second cap structure. The first cap structure is made of a transparent material and located above a backlight module. The light covering layer covers the first cap structure and has a patterned hollow area that defines a transparent character area on the first cap structure. The second cap structure has a transmittance lower than that of the first cap structure, and is disposed above the first cap structure to cover the light covering layer. When the backlight module is not switched on, the transparent character area is not visible through the second cap structure. When the backlight module is switched on, light emitted from the backlight module passes through the second cap structure, and the transparent character area is visible through the second cap structure.

Abstract: Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.

Abstract: An accuracy measurement kit is provided and includes a marker, at least one light beam device, an image capture device, and a processing device. The marker is disposed on an autonomous mobile vehicle, and at least partially includes a reference pattern. The light beam device is configured to emit a light beam to the autonomous mobile vehicle located at a predetermined position so as to form a light spot on the marker. The processing device is configured to capture the light spot the marker on the autonomous mobile vehicle for generating a to-be-analyzed image. The processing device is configured to obtain an offset of the autonomous mobile vehicle in an X-axis direction and a Y-axis direction by calculating images of the to-be-analyzed image corresponding to the reference pattern and the light spot.

Abstract: Embodiments described herein relate to tethered phosphine-borane catalyst complexes for the polymerization of one or more epoxides and one or more of CO2, COS, and CS2. The catalysts can also polymerize cyclic monomers such as lactones and lactide.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a gate structure wrapping around each of the channel layers, a first epitaxial feature abutting a topmost channel layer, a second epitaxial feature disposed directly under the first epitaxial feature, and a separation layer disposed between the first and second epitaxial features. The separation layer and the second epitaxial feature separate the first epitaxial feature from contacting at least a bottommost channel layer.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: A vehicle bracket includes a base, a connecting piece and a fixing piece. A first surface of the base is configured to face a mounting surface. The base has a set of pivoting portions and a set of abutting portions on a second surface thereof. The set of abutting portions is configured to abut against a portion of a vehicle device. A first end of the connecting piece is rotationally and pivotally connected to the set of pivoting portions, and a second end thereof has a rod portion protruding laterally from the connecting piece. The rod portion is configured to be inserted into a guide groove of the vehicle device, so that the rod portion is limited to slide in the guide groove. The fixing piece is configured to fix the set of abutting portions and the portion of the vehicle device to each other.

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The semiconductor device structure includes an isolation structure over the base and surrounding a lower portion of the fin structure. The semiconductor device structure includes a gate stack wrapped around an upper portion of the fin structure. The semiconductor device structure includes a source/drain structure partially embedded in the isolation structure and the lower portion of the fin structure. The source/drain structure has an undoped semiconductor layer and a first doped layer over the undoped semiconductor layer, and the undoped semiconductor layer separates the first doped layer from the isolation structure.