Abstract: The invention provides a memory combination lock, which includes a lock base, a set knob, a stopper, a set of dial unit, a spring, a spindle and a upper case, wherein, the set of the dial unit having several rotary disks, lock bushings and limit plates. A small through hole with an opening is disposed in the lock busing. A corresponding groove on outer wall of the lock bushing is corresponding to the opening. An inlay protruding from a passing hole respectively on the limit plates is embedded in the corresponding groove of lock bushings. There are ten types of limit plates with a limit protrusion respectively disposed on the outer wall thereof and the position of the protrusion is corresponding to one of the ten digits (0˜9) on rotary discs so a set of inner codes is set by a combination of the limit plates with locking bushings.

Abstract: The present invention provides a memory combination lock including a lock base, a set knob, a stopper, a set of dial units, a spring, a spindle, and an upper case. The set of dial units is composed of several rotary disks and several lock bushings. Each of the lock bushings is respectively inserted inside of the rotary disks. Each of the lock bushing has a big through hole and a small through hole with an opening disposed therein. A corresponding groove which position is responding to one of the ten digits (0˜9) on each of the rotary discs respectively is designed on the outer wall surface of ten different types of the lock bushings. Therefore, a set of inner code can be formed by different types of the locking bushings inside of the combination lock and the code can be used to retrieve the password in case of forgetting.

Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

Abstract: A polymer composite for preparing a low dielectric resin composition having a dielectric loss tangent (Df) that is less than or equal to 0.00200 is provided. The polymer composite includes a first styrene-based copolymer having a weight average molecular weight that is lower than 20,000 g/mol and a second styrene-based copolymer having a weight average molecular weight that is higher than 20,000 g/mol, wherein the weight ratio of the first styrene-based copolymer to the second styrene-based copolymer is from 5/95 to 95/5.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Abstract: A variable resistor and a digital-to-analog converter are provided. The variable resistor includes a main resistor, a plurality of switches, and a plurality of redundancy resistors. The switches are respectively constituted by a plurality of non-volatile memory cells. The switches are coupled to the main resistor. The redundancy resistors are respectively coupled to the main resistor through the switches.

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: A light-emitting module of an illuminated keyboard includes a reflector plate, a light guiding plate, a light shielding plate, a base plate, a thin film circuit board, and a light-emitting element. The light guiding plate is disposed on the reflector plate. The light shielding plate is disposed on the light guiding plate and includes a through hole and a first light-passing hole that is spaced apart from the through hole. The base plate is disposed on the light shielding plate and includes an accommodating hole that is aligned with the through hole and a second light-passing hole that is spaced part from the accommodating hole and that is aligned with the first light-passing hole. The thin film circuit board is disposed on the base plate. The light-emitting element is disposed on the thin film circuit board and extends into the accommodating hole.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.

Abstract: Provided is an immunogenic composition including a peptide, wherein consecutive amino acids of the peptide include at least amino acids of SEQ ID NO:1 and one or more adjuvant.

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: This invention relates to a process to produce an ionomer comprising: 1) contacting, in a reactor, one or more C2-C60 ?-olefins, an optional diene, and a metal alkenyl with a catalyst system comprising an activator, a catalyst compound, and a support; 2) forming a copolymer comprising one or more C2-C60 ?-olefin monomers and about 0.01 wt % to about 20 wt %, based on the weight of the copolymer, of metal alkenyl; 3) functionalizing and quenching the polymerization reaction with one or more electrophilic groups; and 4) obtaining ionomer.

Abstract: An aspheric lens includes a treatment zone through which light passes to image at the retina of eyeball and a positioning zone of non-visual area outside treatment zone. The treatment zone includes a base curve and a reverse curve formed on outside of base curve. The positioning zone includes an alignment curve and a peripheral curve located outside alignment curve. A center point is formed in center of base curve, the junction of base curve and reverse curve forms a first point of intersection, the junction of reverse curve and alignment curve forms a second point of intersection, and the junction of alignment curve and peripheral curve forms a third point of intersection. The linear distance between the center point and the cornea of the preset eyeball is between 9 ?m˜21 ?m. The linear distance between the first point of intersection and the cornea of the preset eyeball is between 89 ?m˜189 ?m.