Patents by Inventor Pin Lin

Pin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935841
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
  • Publication number: 20240084450
    Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: HUAN-CHIEH CHEN, JHIH-REN LIN, TAI-PIN LIU, SHYUE-SHIN TSAI, KEITH KUANG-KUO KOAI
  • Publication number: 20240082642
    Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240084056
    Abstract: Elastomeric polyolefin-based ionomers and methods for making same. The ionomers can include a copolymer comprising: C2-C60 ?-olefin monomer units; optional C2-C60 ?-olefin comonomer units different than the monomer units; optional diene units; and about 0.1 wt % to about 20 wt % metal alkenyl units, based on the weight of the copolymer, wherein the metal alkenyl units have the formula —R(A?)—, wherein R is an alkyl group containing 2 to 10 carbon atoms, and A? is an anionic group. The copolymer can further include one or more metal cations derived from the group consisting of alkali metals, alkaline earth metals, group 3-12 metals, group 13-16 metals, and combination(s) thereof. The ionomer has a glass transition temperature of ?60° C. to 5° C., and a weight average (Mw) of 50 to 5,000 kg/mol.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 14, 2024
    Inventors: Tzu-Pin Lin, Carlos R. Lopez-Barron, Avery R. Smith, Brian J. Rohde, Alex E. Carpenter, Matthew W. Holtcamp, Jo Ann M. Canich, John R. Hagadorn
  • Publication number: 20240087980
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Publication number: 20240082640
    Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240085613
    Abstract: A backlight module includes a light guide plate, a light source, a first prism sheet, and a second prism sheet. The light source is disposed on a light incident surface of the light guide plate. The first prism sheet is disposed on a side of a light exiting surface of the light guide plate and has multiple first prism structures facing the light guide plate. The second prism sheet has multiple second prism structures facing the light guide plate. An included angle between an extending direction of the first prism structures and an extending direction of the second prism structures is greater than or equal to 85 degrees and less than or equal to 95 degrees. An included angle between the extending direction of the second prism structures and the light incident surface is greater than or equal to 85 degrees and less than or equal to 95 degrees.
    Type: Application
    Filed: July 26, 2023
    Publication date: March 14, 2024
    Applicants: Coretronic Optics (Suzhou) Co., Ltd., Coretronic Corporation
    Inventors: Chun-Hsiang Hsu, Yen-Hao Lin, Wen-Pin Yang
  • Patent number: 11928132
    Abstract: Provided are a database processing method and apparatus, and a computer readable storage medium. The database processing method comprises: after a lock wait is generated, writing lock wait related information into a lock wait log.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Pin Lin, Yan Ding, Qinyuan Lu, Chen Qi, Yifang Yu, Pei Zhao
  • Patent number: 11925668
    Abstract: Disclosed herein is a process for producing a postbiotic extract, which includes providing a first material having a first isoelectric point ranging from pH 1 to pH 6 and a second material having a second isoelectric point ranging from pH 4 to pH 8, admixing the first material and a probiotic microorganism with water having a pH greater than the second isoelectric point, so as to form a mixture, adding the second material into the mixture and then adjusting a pH of the second material-added mixture to between the first and second isoelectric points so that a precipitate is formed, and subjecting the precipitate to a cell wall isolation treatment to obtain the postbiotic extract. Use of the postbiotic extract is also disclosed.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: March 12, 2024
    Assignee: CHAMBIO CO., LTD.
    Inventors: Meei-Yn Lin, Hung-Pin Chiu, Yi-Heng Chiu
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Publication number: 20240079483
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
  • Patent number: 11923310
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Publication number: 20240065765
    Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: Alvin Chao-Yu CHEN, Yi-Sheng CHAN, Chi-Pin HSU, Shang-Chih LIN, Chin-Ju WU, Jeng-Ywan JENG
  • Patent number: 11910564
    Abstract: A liquid cooling device includes a thermally conductive base, a cover, and a metallic partition. The thermally conductive base has a fluid chamber and a plurality of fins. The fins are located in the fluid chamber and protrudes from an inner surface of the thermally conductive base facing the fluid chamber. Every two of the fins located adjacent to each other define a channel therebetween. Distal ends of at least part of the fins located away from the inner surface together form a covering structure partially coving the channels. The metallic partition is located between and welded to the covering structure and the cover.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: February 20, 2024
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Wei-Pin Lin, Zhong-Long Zhu, Yi-Cheng Chen
  • Patent number: 11901236
    Abstract: An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20240047518
    Abstract: A method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. The method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. The method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20240047546
    Abstract: An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Lun CHANG, Wei-Yang LEE, Chia-Pin LIN
  • Patent number: 11894201
    Abstract: An illuminated keyboard includes a supporting plate, a bottom circuit membrane disposed on the support plate, an intermediate partition plate disposed above the bottom circuit membrane, and a top circuit membrane disposed above said intermediate partition plate. A light emitter unit is disposed on the bottom circuit membrane. A light diffusion layer is disposed above the top circuit membrane and has a light transmission region for transmitting light rays generated from the light emitter unit. An elastic member is made of an elastic material and disposed on and above the diffusion layer. A bridging unit is disposed above the diffusion layer and aligned with the elastic member. A keycap is disposed above and connected to the bridging unit. The elastic member elastically abuts against the keycap. The keycap is light permeable.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: February 6, 2024
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Shih-Pin Lin, Chao-Chieh Yang