Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: The present invention provides a frame transmission method of an electronic device, wherein the frame transmission method includes the steps of: receiving a pause frame from another electronic device, wherein the pause frame includes a plurality of inter frame gap control indicator, and each of the inter frame gap control indicator includes a plurality of packet size ranges and corresponding pause times; selecting one of the inter frame gap control indicator according to a priority of a first packet to be sent to the other electronic device, and determining a first inter frame gap according to which packet size range the first packet belongs to; and after a first frame including the first packet is sent to the other electronic device, at least waiting for the first inter frame gap before starting to send a second frame to the other electronic device.

Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

Abstract: Systems, devices, apparatuses, components, methods, and techniques for media a simple user interface that can facilitate discovery of contextually relevant media content with minimal navigation are provided. For example, the disclosed user interface may present contextually relevant categories, sub-categories and media content items while concurrently playing a media content item predicted to likely be selected by the user.

Abstract: A bicycle lock has a horseshoe lock with a base; and a steel cable. The base has a lock seat, a shell disposes on the base, the shell has a cover to hood on the lock seat, a lock core disposes on the lock seat, a swivel seat assembles on the lock core, a torsion spring disposes between the lock core and the swivel seat, a lock column disposes in an accommodating groove of the shell, a stretch spring disposes in the accommodating groove and sleeves on the lock column and the shell, a butt member disposes in the accommodating groove, a first compression spring disposes in the accommodating groove and sleeves on the shell and in the butt member, a second compression spring disposes in an accommodating groove of the lock seat. The steel cable has a lock rod to insert into the shell and the lock seat.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Abstract: An inductive device and a method of manufacturing the same are provided. The inductive device includes a magnetic base, a coil structure, and a package structure. The magnetic base includes a bottom plate, a core column, and a lateral wall defining a positioning trench. The coil structure includes a coil body, a first extending section, and a second extending section. The coil body disposed in the positioning trench surrounds the core column. The first extending section includes a first bent portion and a first terminal portion connected at a first connecting point. The second extending section includes a second bent portion and a second terminal portion connected at a second connecting point. A shortest distance between a first imaginary connection line defined between the first and second connecting points and a central axis of the core column is less than a minimum outer radius of the coil body.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.

Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: A folding lock comprises a folding plate assembly, a lock seat, a fixing sleeve, a lock core seat, a lock core, a connecting swivel, a lock column, and a fixing collar. A fixed folding plate of the assembly is provided with a connecting seat, the lock seat is disposed on the connecting seat and provided with an insertion hole, an inlay protrudes from the insertion hole, the fixing sleeve inserts into the connecting seat and disposes in the lock seat, the lock core disposes in the lock core seat, the connecting swivel is assembled on the lock core seat, a torsion spring disposes between the lock core seat and the connecting swivel, the lock column is assembled on the connecting swivel, a compression spring is sleeved on the connecting swivel and the lock column, and the fixing collar is disposed in the fixing sleeve.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure that provides a silicon-on-insulator substrate. The semiconductor structure may be formed by providing a base substrate, forming a sacrificial layer over the base structure, and forming a semiconductor layer over the sacrificial layer. The sacrificial layer is removed to form a void that is filled with oxide. The semiconductor structure includes a dielectric support feature extending through the semiconductor and oxide layers and/or a portion of the oxide layer extends to the surface of the semiconductor layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

Abstract: A composition, including: a copolymer including units derived from ethylene, one or more ?-olefins, one or more substituted styrene compounds, and a pendant alkoxy silane group. A method was disclosed to incorporate pendant alkoxy silyl groups onto the benzylic positions. The silane-functionalized polymers show ability to cure with water. Additionally, blends of silane-functionalized polymers exhibit improved filler acceptance.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.