Abstract: A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.

Abstract: An improved and new apparatus and process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the slurry concentration between the wafer and polishing pad is controlled through the application of an electric field between the wafer carrier and polishing platen, has been developed. The result is an increased polish removal rate and better uniformity of the planarization process.

Abstract: A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The high resistance contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation at the high resistance contact region into the metal which will be used to form the metal silicide low resistance contacts converts the metal at the high resistance contact region to metal nitride. Since all the metal at the high resistance contact region is converted to metal nitride there is no free metal to form metal silicide at the high resistance contact region when the low resistance metal silicide contacts are formed. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

Abstract: A process for preventing the formation of precipitates on a substrate surface containing Ti (e.g., TiN) after a contact layer (e.g., tungsten layer) etch back. The process involves treating the wafer with an oxygen plasma etch after the tungsten etch back to remove the precursors of a precipitate. The oxygen plasma etch is performed at temperature of about 260.degree. C. and a pressure about 4 torr.

Abstract: A method is described for fabricating a lightly doped drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode continues by annealing the gate oxide, the polysilicon layer and the metal silicide layer using a furnace process at a temperature more than about 920.degree. C. and for a time of less than about 40 minutes. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The pattern of lightly doped regions is driven in while maintaining the low temperature silicon oxide over the metal silicide layer by annealing at a temperature of more than about 920.degree. C. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer.