Patents by Inventor Pin-To Yao
Pin-To Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958813Abstract: A uracil compound containing a carboxylate fragment, a preparation method therefor, and a herbicidal composition and use thereof are provided. The preparation method includes a contact reaction between a carboxylic acid compound and different substituted alcohol, halogenated, or sulfonate compound in a presence of a solvent. The uracil compound containing a carboxylate fragment provided by the present invention has better herbicidal activity compared with the prior art.Type: GrantFiled: February 5, 2022Date of Patent: April 16, 2024Assignee: JIANGSU FLAG CHEMICAL INDUSTRY CO., LTD.Inventors: Pu Zhang, Kaicheng Yao, Yaojun Wu, Dan Xu, Pin Qian, Long Bu, Congqiang Bai
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Patent number: 11948840Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.Type: GrantFiled: August 31, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
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Patent number: 10770159Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.Type: GrantFiled: July 4, 2018Date of Patent: September 8, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsai-Yu Huang, Pin-Yao Wang
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Patent number: 10242950Abstract: A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.Type: GrantFiled: June 23, 2017Date of Patent: March 26, 2019Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Patent number: 10214483Abstract: The present invention provides a titanium-silicalite molecular sieve and a method for preparing the same. The method includes the steps of preparing a mixture of a titanium source, a silicon source, a metal source selected from IIA to IVA elements and a template agent; heating the mixture to form a gel mixture; heating the gel mixture in a water bath; and calcining the gel mixture after the gel mixture in the water bath to form the titanium-silicalite molecular sieve. The present invention further provides a method for preparing cyclohexanone oxime by using the titanium-silicalite molecular sieve as the catalyst which results in high conversion rate, high selectivity and high usage efficiency of hydrogen peroxide.Type: GrantFiled: August 19, 2016Date of Patent: February 26, 2019Assignee: China Petrochemical Development CorporationInventors: Ya-Ping Chen, Cheng-Fa Hsieh, Pin-To Yao, Chien-Chang Chiang
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Publication number: 20190057754Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.Type: ApplicationFiled: July 4, 2018Publication date: February 21, 2019Inventors: Tsai-Yu Huang, Pin-Yao Wang
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Patent number: 10141035Abstract: The memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor. The read selection transistor has a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.Type: GrantFiled: August 8, 2017Date of Patent: November 27, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsai-Yu Huang, Pin-Yao Wang
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Patent number: 9935116Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: GrantFiled: August 9, 2017Date of Patent: April 3, 2018Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Publication number: 20170373015Abstract: A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.Type: ApplicationFiled: June 23, 2017Publication date: December 28, 2017Inventors: Masaru YANO, Pin-Yao WANG
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Publication number: 20170358589Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: ApplicationFiled: August 9, 2017Publication date: December 14, 2017Applicant: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Patent number: 9786376Abstract: A non-volatile semiconductor memory device achieving low power consumption and erasing method thereof is provided. The flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. When the block of the selected global block is erased and the next block is in adjacent relationship, electric charge accumulated in one of P-wells is discharged to another one of the P-wells, and then the next selected block is erased. Thus, the electric charge is shared between the adjacent P-wells to achieve low power consumption.Type: GrantFiled: April 28, 2016Date of Patent: October 10, 2017Assignee: Winbond Electronics Corp.Inventor: Pin-Yao Wang
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Patent number: 9768184Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: GrantFiled: August 16, 2016Date of Patent: September 19, 2017Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Publication number: 20170133094Abstract: A non-volatile semiconductor memory device achieving low power consumption and erasing method thereof is provided. The flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. When the block of the selected global block is erased and the next block is in adjacent relationship, electric charge accumulated in one of P-wells is discharged to another one of the P-wells, and then the next selected block is erased. Thus, the electric charge is shared between the adjacent P-wells to achieve low power consumption.Type: ApplicationFiled: April 28, 2016Publication date: May 11, 2017Inventor: Pin-Yao Wang
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Publication number: 20160358929Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Applicant: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Publication number: 20160355467Abstract: The present invention provides a titanium-silicalite molecular sieve and a method for preparing the same. The method includes the steps of preparing a mixture of a titanium source, a silicon source, a metal source selected from IIA to IVA elements and a template agent; heating the mixture to form a gel mixture; heating the gel mixture in a water bath; and calcining the gel mixture after the gel mixture in the water bath to form the titanium-silicalite molecular sieve. The present invention further provides a method for preparing cyclohexanone oxime by using the titanium-silicalite molecular sieve as the catalyst which results in high conversion rate, high selectivity and high usage efficiency of hydrogen peroxide.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Inventors: Ya-Ping Chen, Cheng-Fa Hsieh, Pin-To Yao, Chien-Chang Chiang
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Patent number: 9449697Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: GrantFiled: February 12, 2015Date of Patent: September 20, 2016Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Pin-Yao Wang
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Patent number: 9434683Abstract: The present invention provides a titanium-silicalite molecular sieve and a method for preparing the same. The method includes the steps of preparing a mixture of a titanium source, a silicon source, a metal source selected from IIA to IVA elements and a template agent; heating the mixture to form a gel mixture; heating the gel mixture in a water bath; and calcining the gel mixture after the gel mixture in the water bath to form the titanium-silicalite molecular sieve. The present invention further provides a method for preparing cyclohexanone oxime by using the titanium-silicalite molecular sieve as the catalyst which results in high conversion rate, high selectivity and high usage efficiency of hydrogen peroxide.Type: GrantFiled: January 13, 2012Date of Patent: September 6, 2016Assignee: China Petrochemical Development CorporationInventors: Ya-Ping Chen, Cheng-Fa Hsieh, Pin-To Yao, Chien-Chang Chiang
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Patent number: 9371238Abstract: The present invention provides a titanium-silicalite molecular sieve and a method for preparing the same. The method includes the steps of preparing a mixture of a titanium source, a silicon source, a transition metal source, a template agent and water; heating the mixture to form a gel mixture; heating the gel mixture in a water bath; and calcining the gel mixture after the gel mixture in the water bath to form the titanium-silicalite molecular sieve. The present invention further provides a method for preparing cyclohexanone oxime by using the titanium-silicalite molecular sieve as the catalyst which results in high conversion rate, high selectivity and high usage efficiency of hydrogen peroxide.Type: GrantFiled: January 6, 2012Date of Patent: June 21, 2016Assignee: China Petrochemical Development CorporationInventors: Ya-Ping Chen, Cheng-Fa Hsieh, Pin-To Yao, Chien-Chang Chiang
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Publication number: 20150380092Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).Type: ApplicationFiled: February 12, 2015Publication date: December 31, 2015Inventors: Masaru Yano, Pin-Yao Wang
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Patent number: 9206101Abstract: A method for hydroxylation of phenol is disclosed. The method includes the step of performing a reaction of phenol and hydrogen peroxide to form diphenol in the presence of solid catalyst with zeolite framework, wherein the solid catalyst includes silicon oxide, titanium oxide and cobalt oxide. The solid catalyst used in the preparation of diphenol of the present invention has high conversion rate of diphenol, selectivity of diphenol and higher utilization rate of hydrogen peroxide without using high concentration of hydrogen peroxide.Type: GrantFiled: October 2, 2013Date of Patent: December 8, 2015Assignee: China Petrochemical Development CorporationInventors: I-Hui Lin, Cheng-Fa Hsieh, Pin-To Yao