Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a number of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a number of conductive spacers is formed. A number of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: A method for preparing hydroxylamine, comprising the steps of: (i) pretreating the acidic buffer solution with the compounds having a functional group represented by formula (I), thereby removing metal impurities from the acidic buffer solution; and (ii) reducing nitrate ions in the acidic buffer solution with hydrogen to give hydroxylamine in the presence of catalysts, According to the present invention the selectivity for reducing nitrate ions to give hydroxylamine can be significantly enhanced.

Abstract: A substrate having a first dielectric layer, a first conductive layer and a second dielectric layer thereon is provided. A part of the second dielectric layer is removed to form a first opening having both ends with a select gate region respectively. The select gate region is constituted by a region with the second dielectric layer and a region without the second dielectric layer. A second conductive layer is formed to cover the second dielectric layer. A cap layer is formed on the second conductive layer. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer are patterned to form gate structures. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer between two adjacent select gate regions are removed to form a select gate structure. A doped region is formed in the substrate.

Abstract: A method for fabricating a conductive line is provided. First, a substrate having at least two isolation structures already formed is provided. A first conductive layer is formed between every two isolation structures. Then, a dielectric layer is formed on the substrate. The dielectric layer is patterned to form an opening exposing the first conductive layer. After that, a second conductive layer is formed on the substrate. A portion of the second conductive layer outside the opening is removed to form a conductive line. As the size of the device is getting smaller, the size and the position accuracy of the conductive line would not be limited to the design rules of lithography if the present invention is applied. Therefore, a conductive line is formed to electrically connect semiconductor devices effectively.

Abstract: A substrate having a first dielectric layer, a first conductive layer and a second dielectric layer thereon is provided. A part of the second dielectric layer is removed to form a first opening having both ends with a select gate region respectively. The select gate region is constituted by a region with the second dielectric layer and a region without the second dielectric layer. A second conductive layer is formed to cover the second dielectric layer. A cap layer is formed on the second conductive layer. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer are patterned to form gate structures. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer between two adjacent select gate regions are removed to form a select gate structure. A doped region is formed in the substrate.

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.

Abstract: A non-volatile memory includes a substrate, a plurality of isolation layers, a plurality of active layers, a plurality of floating gates, a plurality of control gates and a plurality of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates.

Abstract: A non-volatile memory structure including a substrate, a first memory cell row, a first source/drain region, and a second source/drain region is described. The first memory cell row is disposed on the substrate and includes a plurality of memory cells, two select gate structures, and a plurality of doped regions. The select gate structures are respectively disposed on the substrate at one side of the outmost memory cell among the memory cells, and the select gates have a tapered corner at one side far from the memory cells. The doped regions are respectively disposed in the substrate between two memory cells as well as in the substrate between the memory cells and the select gate structures. The first and the second source/drain regions are respectively disposed in the substrate at both sides of the first memory cell row.

Abstract: A method for fabricating a conductive line is provided. First, a substrate having at least two isolation structures already formed is provided. A first conductive layer is formed between every two isolation structures. Then, a dielectric layer is formed on the substrate. The dielectric layer is patterned to form an opening exposing the first conductive layer. After that, a second conductive layer is formed on the substrate. A portion of the second conductive layer outside the opening is removed to form a conductive line. As the size of the device is getting smaller, the size and the position accuracy of the conductive line would not be limited to the design rules of lithography if the present invention is applied. Therefore, a conductive line is formed to electrically connect semiconductor devices effectively.

Abstract: An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.

Abstract: A non-volatile memory having a substrate, a select gate, a pair of charge storage layers, a pair of source/drain regions and a control gate is provided. At least a pair of trenches are formed in the substrate. The select gate is formed on the substrate between the pair of trenches. A pair of charge storage layers is formed on the sidewalls of the trenches next to the select gate. A pair of source/drain regions is formed in the substrate at the bottom of the trenches. The control gate is formed on the substrate to fill the trenches completely.

Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a plurality of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a plurality of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a plurality of conductive spacers is formed. A plurality of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: A method of manufacturing a shallow trench isolation structure adapted for a substrate, is provided. A dielectric film is formed on the substrate and then a buffer layer having a first thickness is formed on the dielectric film. Then, a hard mask layer having a second thickness is formed on the buffer layer. The hard mask layer, the buffer layer, the dielectric film and the substrate are patterned to form an opening in the hard mask layer, the buffer layer and the dielectric film and a trench in the substrate. An insulating layer is formed to fill up the opening and the trench. Thereafter, the hard mask layer, a portion of the insulating layer and the buffer layer are removed to form a shallow trench isolation structure that protrudes out of the substrate surface.

Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.

Abstract: A method of forming contact holes is provided. A substrate having a plurality of device structures is provided. A first dielectric layer and a conductive layer sequentially cover the device structures and the surface of the substrate. A recess is formed in the conductive layer between every two neighboring device structures. A pair of composite spacers is formed in the recess. By using the composite spacers as a mask, a portion of the exposed conductive layer is removed to form a plurality of openings between every two neighboring device structures. A second dielectric layer is then formed on the sidewalls of the openings. A third dielectric layer is formed over the substrate. Portions of the third dielectric layer and the first dielectric layer above the openings are removed to form a plurality of self-aligned contact holes.

Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.

Abstract: A method of forming contact holes is provided. A substrate having a plurality of device structures is provided. A first dielectric layer and a conductive layer sequentially cover the device structures and the surface of the substrate. A recess is formed in the conductive layer between every two neighboring device structures. A pair of composite spacers is formed in the recess. By using the composite spacers as a mask, a portion of the exposed conductive layer is removed to form a plurality of openings between every two neighboring device structures. A second dielectric layer is then formed on the sidewalls of the openings. A third dielectric layer is formed over the substrate. Portions of the third dielectric layer and the first dielectric layer above the openings are removed to form a plurality of self-aligned contact holes.

Abstract: A method of fabricating a flash memory cell is provided. The method includes providing a substrate and forming a patterned mask layer over the substrate. Using the patterned mask layer as an etching mask, the substrate is etched to form a trench. Thereafter, a first dielectric layer is formed over the substrate and then a first gate and a second gate is formed beside each sidewall of the trench. A first source/drain region is formed in the substrate at the bottom of the trench. A second dielectric layer is formed over the substrate and then a passivation layer is formed over the second dielectric layer. Afterwards, a portion of the passivation layer, the second dielectric layer and the first dielectric layer are removed. A third gate is formed in the trench and then the mask layer is removed. A third dielectric layer is formed on the substrate. Thereafter, a fourth and a fifth gate are formed beside the respective sidewall of the first gate and the second gate.

Abstract: A method of fabricating a flash memory cell is provided. The method includes providing a substrate and forming a patterned mask layer over the substrate. Using the patterned mask layer as an etching mask, the substrate is etched to form a trench. Thereafter, a first dielectric layer is formed over the substrate and then a first gate and a second gate is formed beside each sidewall of the trench. A first source/drain region is formed in the substrate at the bottom of the trench. A second dielectric layer is formed over the substrate and then a passivation layer is formed over the second dielectric layer. Afterwards, a portion of the passivation layer, the second dielectric layer and the first dielectric layer are removed. A third gate is formed in the trench and then the mask layer is removed. A third dielectric layer is formed on the substrate. Thereafter, a fourth and a fifth gate are formed beside the respective sidewall of the first gate and the second gate.