Patents by Inventor PIN-WEN CHEN
PIN-WEN CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220130819Abstract: A semiconductor chip includes a metal-oxide-semiconductor (MOS) transistor, a first oxide protection circuit, and a second oxide protection circuit. The first oxide protection circuit has a first terminal coupled to a gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first ground voltage, wherein a noise level of the first ground voltage is lower than a noise level of a second ground voltage defined in the semiconductor chip. The second oxide protection circuit has a first terminal coupled to the gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first supply voltage, wherein a noise level of the first supply voltage is lower than a noise level of a second supply voltage defined in the semiconductor chip.Type: ApplicationFiled: September 22, 2021Publication date: April 28, 2022Applicant: MEDIATEK INC.Inventor: Pin-Wen Chen
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Publication number: 20210193517Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
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Patent number: 11020446Abstract: A method for preparing a tea leaf extract is used for preparing the tea leaf extract with improved anti-oxidation activity. The method includes smoldering a rice husk sample at 200-400° C. in a low oxygen environment for 2-4 hours, followed by burning at 400-600° C. in an atmospheric environment for 2-4 hours to obtain a rice husk silica. An oxygen concentration in the low oxygen environment is below 5%. The rice husk silica is dissolved in an alkaline solution to obtain a rice husk silica solution. A tea leaf sample is then extracted by the rice husk silica solution.Type: GrantFiled: September 18, 2018Date of Patent: June 1, 2021Assignee: GREENEPIC BIOTECH CORPORATIONInventors: Yung-Han Hung, Pin-Wen Chen, Yu-Tsai Chen
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Publication number: 20210074580Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10943823Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: GrantFiled: October 16, 2019Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
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Patent number: 10847411Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: GrantFiled: August 30, 2019Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Publication number: 20200343135Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 10804140Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: GrantFiled: March 29, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Publication number: 20200176382Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: ApplicationFiled: November 13, 2019Publication date: June 4, 2020Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-jung Lin, Chih-Wei Chang
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Publication number: 20200051858Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
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Publication number: 20190385904Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10475702Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: GrantFiled: March 14, 2018Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Wang, Ya-Yi Cheng, I-Li Chen
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Publication number: 20190304833Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen CHEN, Chia-Han LAI, Mei-Hui FU, Min-Hsiu HUNG, Ya-Yi CHENG
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Publication number: 20190287851Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen CHEN, Chia-Han LAI, Chih-Wei CHANG, Mei-Hui FU, Ming-Hsing TSAI, Wei-Jung LIN, Yu Shih WANG, Ya-Yi CHENG, I-Li CHEN
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Patent number: 10373907Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.Type: GrantFiled: February 15, 2018Date of Patent: August 6, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pin-Wen Chen, Chih-Wei Chang
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Publication number: 20190224265Abstract: A method for preparing a tea leaf extract is used for preparing the tea leaf extract with improved anti-oxidation activity. The method includes smoldering a rice husk sample at 200-400° C. in a low oxygen environment for 2-4 hours, followed by burning at 400-600° C. in an atmospheric environment for 2-4 hours to obtain a rice husk silica. An oxygen concentration in the low oxygen environment is below 5%. The rice husk silica is dissolved in an alkaline solution to obtain a rice husk silica solution. A tea leaf sample is then extracted by the rice husk silica solution.Type: ApplicationFiled: September 18, 2018Publication date: July 25, 2019Inventors: Yung-Han HUNG, Pin-Wen CHEN, Yu-Tsai CHEN
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Publication number: 20180174963Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Pin-Wen Chen, Chih-Wei Chang
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Patent number: 9917051Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.Type: GrantFiled: January 24, 2017Date of Patent: March 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pin-Wen Chen, Chih-Wei Chang
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Patent number: 9844322Abstract: A camera device configured to obtain an image of an eye is provided. The camera apparatus includes an image sensing unit, a lens set, and a processing unit. The lens set is located between the image sensing unit and the eye and projects light from the eye to the image sensing unit. Here, the lens set and the image sensing unit correspondingly move relative to the eye and continuously shoot a plurality of images of a plurality of parts of the eye. The processing unit is electrically connected to the image sensing unit, and the processing unit stitches the images. A photographing method is also provided.Type: GrantFiled: February 27, 2013Date of Patent: December 19, 2017Assignee: ALTEK BIOTECHNOLOGY CORPORATIONInventors: Shin-Hao Cheng, Pin-Wen Chen
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Publication number: 20170133318Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Inventors: Pin-Wen Chen, Chih-Wei Chang