Abstract: A programmable logic device uses power island based design partitioning. Each power islands includes a plurality of programmable logic cells and a programmable routing network configurable to interconnect the plurality of programmable logic cells and configurable to interconnect with at least one other power island. When a power island is in an OFF state, the programmable logic cells within the power island are powered OFF. Feed-through routing connectors in the power island, however, may be statically or dynamically powered ON independently of the powered OFF state of the power island.

Abstract: A programmable logic device uses power island based design partitioning. Each power islands includes a plurality of programmable logic cells and a programmable routing network configurable to interconnect the plurality of programmable logic cells and configurable to interconnect with at least one other power island. When a power island is in an OFF state, the programmable logic cells within the power island are powered OFF. Feed-through routing connectors in the power island, however, may be statically or dynamically powered ON independently of the powered OFF state of the power island.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.

Abstract: A computer implemented method for designing an integrated circuit includes receiving a netlist. The method also includes receiving physical layout information related to an integrated circuit based on the on the netlist and receiving an engineering change order (ECO) that changes at least one logical component of the physical layout. The method further includes forming two or more possible solutions to achieve the ECO, ranking the two or more possible solutions based on two or more factors and selecting the highest ranked solution.

Abstract: Methods, systems, and computer readable media for providing fuzz testing functionality are disclosed. According to one method, the method includes at a fuzz testing module (FTM), generating a plurality of test messages, including a test message including fuzzed data, generating fuzzed message identification information, and transmitting the test message and the fuzzed message identification information to a device under test (DUT). The method also includes at a packet analyzer located between the FTM and the DUT, receiving the plurality of test messages and the fuzzed message identification information, and identifying the test message including the fuzzed data using the fuzzed message identification information.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.

Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.